AD5555CRU Analog Devices Inc, AD5555CRU Datasheet - Page 6

• Manufacturer Part Number: AD5555CRU
• Description: IC DAC 14BIT DUAL SRL IN 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5555CRU

• Rohs Status: RoHS non-compliant
• Settling Time: 500ns
• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 55µW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP

AD5545/AD5555
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
R
V
I
A
A
I
V
R
SDI
RS
CS
DGND
V
MSB
LDAC
CLK
OUT
OUT
FB
REF
REF
FB
DD
GND
GND
A
B
A
B
A
B
A
B
Description
Establish voltage output for DAC A by connecting this pin to an external amplifier output.
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can
be tied to the V
DAC A Current Output.
DAC A Analog Ground.
DAC B Analog Ground.
DAC B Current Output.
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage.
This pin can be tied to the V
Establish voltage output for DAC B by the R
Serial Data Input. Input data loads directly into the shift register.
Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or midscale. Register
Data = 0x0000 when MSB = 0. Register Data = 0x8000 for AD5545 and 0x2000 for AD5555 when
MSB = 1.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register
data to the input register when CS/LDAC returns high. This does not affect LDAC operation.
Digital Ground Pin.
Positive Power Supply Input. Specified range of operation 5 V ± 10% or 3 V ± 10%.
MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on.
Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can also be tied
permanently to ground or V
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC
registers. Asynchronous active low input. See Table 7 and Table 8 for operation.
Clock Input. Positive edge clocks data into shift register.
A
A
V
V
I
I
R
GND
GND
R
OUT
OUT
REF
REF
FB
FB
A
A
A
A
B
B
B
B
DD
Figure 4. 16-Lead TSSOP
1
2
3
4
5
6
7
8
pin.
Rev. C | Page 6 of 20
(Not to Scale)
AD5545/
AD5555
TOP VIEW
DD
DD
02918- 0- 002
.
pin.
16
15
14
13
12
10
11
9
CLK
LDAC
MSB
V
DGND
CS
RS
SDI
DD
FB
B pin connecting to an external amplifier output.