AD9706BCPZ Analog Devices Inc, AD9706BCPZ Datasheet - Page 35

• Manufacturer Part Number: AD9706BCPZ
• Description: IC DAC TX 12BIT 175MSPS 32-LFCSP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9706BCPZ

• Settling Time: 11ns
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 50mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Inl ±: 1.48LSB
• Update Rate: 175MSPS
• Output Type: Current
• Termination Type: SMD
• Supply Voltage Max: 3.6V
• No. Of Bits: 12 Bit
• Leaded Process Compatible: Yes
• Dnl±: 1.17LSB
• No. Of Dacs: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9706-EBZ - BOARD EVAL FOR AD9706
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Equation 7 and Equation 8 highlight some of the advantages
of operating the AD9704/AD9705/AD9706/AD9707 differentially.
First, the differential operation helps cancel common-mode error
sources associated with IOUTA and IOUTB, such as noise,
distortion, and dc offsets. Second, the differential code depend-
ent current and subsequent voltage, V
the single-ended voltage output (that is, V
providing twice the signal power to the load.
Note that the gain drift temperature performance for a single-
ended output (V
of the AD9704/AD9705/AD9706/AD9707 can be enhanced
by selecting temperature-tracking resistors for R
because of their ratio metric relationship, as shown in Equation 8.
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA, and
IOUTB can be configured for single-ended or differential opera-
tion. IOUTA and IOUTB can be converted into complementary
single-ended voltage outputs, V
resistor, R
section by Equation 5 through Equation 8. The differential
voltage, V
be converted to a single-ended voltage via a transformer or a
differential amplifier configuration. The ac performance of the
AD9704/AD9705/AD9706/AD9707 is optimum and is specified
using a differential transformer-coupled output in which the
voltage swing at IOUTA and IOUTB is limited to ±0.5 V.
The distortion and noise performance of the AD9704/AD9705/
AD9706/AD9707 can be enhanced when it is configured for
differential operation. The common-mode error sources of
both IOUTA and IOUTB can be significantly reduced by the
common-mode rejection of a transformer or differential
amplifier. These common-mode error sources include even-
order distortion products and noise. The enhancement in
distortion performance becomes more significant as the fre-
quency content of the reconstructed waveform increases and/or
its amplitude increases. This is due to the first order cancellation
of various dynamic common-mode distortion mechanisms,
digital feedthrough, and noise.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the
reconstructed signal power to the load (assuming no source
termination). Because the output currents of IOUTA and
IOUTB are complementary, they become additive when
processed differentially.
When the AD9704/AD9705/AD9706/AD9707 is being used at
its nominal operating point of 2 mA output current, and 0.5 V
output swing is desired, R
selected transformer allows the AD9704/AD9705/AD9706/
AD9707 to provide the required power and voltage levels to
different loads.
LOAD
DIFF
, existing between V
, as described in the DAC Transfer Function
IOUTA
and V
LOAD
IOUTB
must be set to 250 Ω. A properly
IOUTA
) or differential output (V
IOUTA
and V
DIFF
and V
, is twice the value of
IOUTA
IOUTB
IOUTB
or V
, via a load
LOAD
, can also
IOUTB
and R
), thus
DIFF
SET
Rev. A | Page 35 of 52
)
,
The output impedance of IOUTA and IOUTB is determined
by the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 200 MΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (that is, V
device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration results in the
optimum dc linearity. Note that the INL/DNL specifications for
the AD9704/AD9705/AD9706/AD9707 are measured with
IOUTA maintained at a virtual ground via an op amp.
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The absolute maximum negative output
compliance range of −1 V is set by the breakdown limits of the
CMOS process. Operation beyond this maximum limit can result
in a breakdown of the output stage and affect the reliability of
the AD9704/AD9705/AD9706/AD9707.
The positive output compliance range is slightly dependent on
the full-scale output current, I
nominal 1.0 V for an I
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V.
ADJUSTABLE OUTPUT COMMON MODE
The AD9704/AD9705/AD9706/AD9707 provide the ability to
set the output common mode to a value other than ACOM via
Pin 19 (OTCM). This extends the compliance range of the
outputs and facilitates interfacing the output of the AD9704/
AD9705/AD9706/AD9707 to components that require common-
mode levels other than 0 V. The OTCM pin demands dynami-
cally changing current and should be driven by a low source
impedance to prevent a common-mode signal from appearing
on the DAC outputs. For optimum performance, set the voltage
on OTCM equal to the center of the output swing on IOUTA
and IOUTB.
Note that setting OTCM to a voltage greater than ACOM allows
the peak of the output signal to be closer to the positive supply
rail. To prevent distortion in the output signal due to limited
available headroom, the common-mode level must be chosen
such that the following expression is satisfied:
DIGITAL INPUTS
The AD9707, AD9706, AD9705, and AD9704 have data inputs
of 14, 12, 10, and 8 bits, respectively, and each has a clock input.
The parallel data inputs can follow standard positive binary or
twos complement coding. IOUTA produces a full-scale output
current when all data bits are at Logic 1. IOUTB produces a
complementary output with the full-scale current split between
the two outputs as a function of the input code.
AVDD − V
AD9704/AD9705/AD9706/AD9707
OTCM
IOUTA
> 1.8 V
OUTFS
and V
= 2 mA to 0.8 V for an I
IOUTB
OUTFS
) due to the nature of a PMOS
. It degrades slightly from its
OUTFS
= 1 mA.
(9)