AD5611AKSZ-500RL7 Analog Devices Inc, AD5611AKSZ-500RL7 Datasheet - Page 4

• Manufacturer Part Number: AD5611AKSZ-500RL7
• Description: IC DAC 10BIT BUFF V-OUT SC70-6
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5611AKSZ-500RL7

• Data Interface: SPI™
• Package / Case: SC-70-6, SC-88, SOT-363
• Mounting Type: Surface Mount
• Power Dissipation (max): 500µW
• Operating Temperature: -40°C ~ 125°C
• Number Of Bits: 10
• Voltage Supply Source: Single Supply
• Settling Time: 6µs
• Number Of Converters: 1
• Resolution (bits): 10bit
• Sampling Rate: 1.7MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 75µA
• Digital Ic Case Style: SC-70
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5601/AD5611/AD5621
Parameter
POWER REQUIREMENTS
POWER EFFICIENCY
1
2
3
4
5
TIMING CHARACTERISTICS
V
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
1
2
1
2
3
4
5
6
7
8
9
Asterisk (*) = specifications same as B grade.
Temperature range for A/B grades is –40°C to +125°C, typical at +25°C.
Linearity calculated using a reduced code range: AD5621 from Code 64 to Code 4032; AD5611 from Code 16 to Code 1008; AD5601 from Code 4 to Code 252.
Guaranteed by design and characterization, not production tested.
Total current flowing into all pins.
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
Maximum SCLK frequency is 30 MHz.
DD
2
V
I
I
I
DD
DD
OUT
DD
= 2.7 V to 5.5 V; all specifications T
V
V
V
V
(Normal Mode)
(All Power-Down Modes)
/I
DD
DD
DD
DD
DD
= ±4.5 V to ±5.5 V
= ±2.7 V to ±3.6 V
= ±4.5 V to ±5.5 V
= ±2.7 V to ±3.6 V
SYNC
SCLK
SDIN
Limit
33
5
5
10
5
4.5
0
20
13
1
t
8
t
4
D15
Min
*
MIN
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
A Grade
to T
Typ
*
*
*
*
*
D14
MAX
t
3
2
, unless otherwise noted. See Figure 2.
1, 2
t
Max
*
*
*
2
DD
) and timed from a voltage level of (V
Figure 2. Timing Diagram
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK falling edge ignored
t
1
Min
2.7
Rev. C | Page 4 of 20
D2
Typ
75
60
0.5
0.2
96
B Grade
t
2
5
D1
t
6
2
Max
5.5
100
90
D0
t
7
IL
t
Unit
V
μA
μA
μA
μA
%
9
+ V
IH
)/2.
Test Conditions/Comments
All digital inputs at 0 V or V
DAC active and excluding load
current
V
V
V
V
V
I
LOAD
IH
IH
IH
IH
IH
D15
= V
= V
= V
= V
= V
= 2 mA and V
DD
DD
DD
DD
DD
and V
and V
and V
and V
and V
D14
IL
IL
IL
IL
IL
= GND
= GND
= GND
= GND
= GND
DD
= ±5 V
DD