LTC2630ISC6-HM10#TRMPBF Linear Technology, LTC2630ISC6-HM10#TRMPBF Datasheet - Page 14

• Manufacturer Part Number: LTC2630ISC6-HM10#TRMPBF
• Description: IC DAC 10BIT R-R SC70-6
• Manufacturer: Linear Technology

Specifications of LTC2630ISC6-HM10#TRMPBF

• Settling Time: 3.9µs
• Number Of Bits: 10
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 480µW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SC-70-6, SC-88, SOT-363
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OPERATION
LTC2630
Serial Interface
The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, enabling the SDI and
SCK buffers and the input shift register. Data (SDI input)
is transferred at the next 24 rising SCK edges. The 4-bit
command, C3-C0, is loaded fi rst; then 4 don’t-care bits;
and fi nally the 16-bit data word. The data word comprises
the 12-, 10- or 8-bit input code, ordered MSB-to-LSB,
followed by 4, 6 or 8 don’t-care bits (LTC2630-12, -10 and
-8 respectively; see Figure 2). Data can only be transferred
to the device when the CS/LD signal is low, beginning on
the fi rst rising edge of SCK. SCK may be high or low at
the falling edge of CS/LD. The rising edge of CS/LD ends
the data transfer and causes the device to execute the
command specifi ed in the 24-bit input sequence. The
complete sequence is shown in Figure 3a.
14
INPUT WORD (LTC2630-12)
INPUT WORD (LTC2630-10)
INPUT WORD (LTC2630-8)
C3
C3
C3
COMMAND
COMMAND
COMMAND
C2
C2
C2
C1
C1
C1
C0
C0
C0
X
X
X
4 DON'T-CARE BITS
4 DON'T-CARE BITS
4 DON'T-CARE BITS
X
X
X
X
X
X
Figure 2. Command and Data Input Format
X
X
X
MSB
MSB
MSB
D11 D10
D9
D7
D8
D6
D9
D7
D5
D8
D6
D4
The command (C3-C0) assignments are shown in Table 1.
The fi rst three commands in the table consist of write and
update operations. A Write operation loads a 16-bit data
word from the 24-bit shift register into the input register.
In an Update operation, the input register is copied to the
DAC register and converted to an analog voltage at the
DAC output. Write to and Update combines the fi rst two
commands. The Update operation also powers up the
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
While the minimum input sequence is 24-bits, it may
optionally be extended to 32-bits to accommodate micro-
processors that have a minimum word width of 16-bits
(2 bytes). To use the 32-bit width, 8 don’t-care bits are trans-
ferred to the device fi rst, followed by the 24-bit sequence
described. Figure 3b shows the 32-bit sequence.
D7
D5
D3
DATA (12 BITS + 4 DON'T-CARE BITS)
DATA (10 BITS + 6 DON'T-CARE BITS)
DATA (8 BITS + 8 DON'T-CARE BITS)
D6
D4
D2
D5
D3
D1
LSB
D4
D2
D0
D3
D1
X
LSB
D2
D0
X
D1
X
X
LSB
D0
X
X
X
X
X
X
X
X
X
X
X
2630 F02
X
X
X
2630fe