MX7837KR+ Maxim Integrated Products, MX7837KR+ Datasheet - Page 7

• Manufacturer Part Number: MX7837KR+
• Description: IC DAC 12BIT DL MULT 24SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MX7837KR+

• Settling Time: 4µs
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 941mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 4. MX7837 Input Control Logic
CS, WR, A0, and A1 control data loading to the input
latches. The eight data inputs accept right-justified
data, which can be loaded to the input latches in any
sequence. If LDAC is held high, loading data to the
input latches will not change the analog output. A0
and A1 determine which input latch will receive the
data when CS and WR are low. Table 2 shows the
control logic truth table.
Table 2. MX7837 Truth Table
X = Don't Care
The LDAC input controls 12-bit data transfer from the
input latches to the DAC latches. When LDAC is taken
low, both DAC latches (thus, both analog outputs) are
updated simultaneously. When LDAC is low, the DAC
latches are transparent; DAC data is latched on the ris-
ing edge of LDAC. The LDAC input is asynchronous
CS WR
1
X
0
0
0
0
1
LDAC
WR
CS
A0
A1
X
1
0
0
0
0
1
A1
X
X
X
0
0
1
1
A0
X
X
X
0
1
0
1
_______________________________________________________________________________________
LDAC
1
1
1
1
1
1
0
No Data Transfer
No Data Transfer
DAC A LS Input Latch Transparent
DAC A MS Input Latch Transparent
DAC B LS Input Latch Transparent
DAC B MS Input Latch Transparent
Updated Simultaneously from
the Respective Input Latches
DAC A
LATCH
INPUT
DAC A LATCH
MS
4
12
DAC A
LATCH
INPUT
LS
8
Function
DB7 DB0
8
LATCH
DAC B
INPUT
MS
DAC B LATCH
4
12
LATCH
DAC B
INPUT
LS
8
and independent of WR. This is useful in many appli-
cations, especially in updating multiple MX7837s simul-
taneously. However, be careful when exercising LDAC
during a write cycle; if an LDAC operation overlaps a
CS and WR operation, invalid data may be latched to
the output. To avoid this, LDAC must remain low after
CS or WR have returned high for a period equal to or
greater than t
Figure 6 shows DAC A (MX7837/MX7847) connected
for unipolar binary operation. Similar connections
apply for DAC B. When V
performs 2-quadrant multiplication. Table 3 shows the
code table for this circuit. On the MX7847, the R
feedback resistor is internally connected to V
Table 3. Unipolar Code Table
Figure 5. MX7837 Write-Cycle Timing Diagram
Note : 1LSB
DAC Latch Contents
Complete, Dual, 12-Bit
A0/A1
LDAC
DATA
WR
CS
MSB
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
8
LSB
Multiplying DACs
, the minimum LDAC pulse width.
t
6
t
1
4096
V
IN
ADDRESS VALID
Unipolar Binary Operation
VALID DATA
0V
V
V
V
t
t
4
3
IN
IN
IN
IN
Analog Output, V
is an AC signal, the circuit
4095
4096
2048
4096
4096
1
t
2
t
5
t
7
t
1
2
8
OUT
V
OUT
IN
.
FB
7