MAX5133AEEE+ Maxim Integrated Products, MAX5133AEEE+ Datasheet - Page 14

• Manufacturer Part Number: MAX5133AEEE+
• Description: IC DAC 13BIT 3V LP SER 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5133AEEE+

• Settling Time: 20µs
• Number Of Bits: 13
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -

Integral nonlinearity (Figure 8a) is the deviation of the
values on an actual transfer function from a straight
line. This straight line can be either a best-straight-line
fit (closest approximation to the actual transfer curve) or
a line drawn between the endpoints of the transfer func-
tion, once offset and gain errors have been nullified. For
a DAC, the deviations are measured at every single
step.
+5V/+3V, 13-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
Table 3. Detailed SSPCON Register Contents
X = Don’t care
Table 4. Detailed SSPSTAT Register Contents
X = Don’t care
14
__________Applications Information
SSPOV
SSPM3
SSPM2
SSPM1
SSPM0
______________________________________________________________________________________
SSPEN
WCOL
SMP
CKP
CKE
R/W
D/A
UA
BF
P
S
CONTROL BIT
CONTROL BIT
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
Integral Nonlinearity (INL)
MAX5132/MAX5133
MAX5132/MAX5133
SETTINGS
SETTINGS
Definitions
X
X
1
0
0
0
0
1
0
1
X
X
X
X
X
X
Write-Collision Detection Bit
Receive-Overflow Detection Bit
Synchronous Serial Port Enable Bit
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI as seri-
al-port pins.
Clock-Polarity Select Bit. CKP = 0 for SPI master-mode selection.
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode
and selects f
SPI Data-Input Sample Phase. Input data is sampled at the mid-
dle of the data-output time.
SPI Clock-Edge Select Bit. Data will be transmitted on the rising
edge of the serial clock.
Data-Address Bit
Stop Bit
Start Bit
Read/Write Bit Information
Update Address
Buffer Full-Status Bit
Differential nonlinearity (Figure 8b) is the difference
between an actual step height and the ideal value of
1LSB. If the magnitude of the DNL is less than or equal to
1LSB, the DAC guarantees no missing codes and is
monotonic.
The offset error (Figure 8c) is the difference between
the ideal and the actual offset point. For a DAC, the off-
set point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated for by trimming.
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
SYNCHRONOUS SERIAL-PORT STATUS REGISTER
CLK
= f
OSC
/ 16.
(SSPSTAT)
(SSPCON)
Differential Nonlinearity (DNL)
Offset Error