MAX517BESA+ Maxim Integrated Products, MAX517BESA+ Datasheet - Page 4

• Manufacturer Part Number: MAX517BESA+
• Description: IC DAC 8BIT SGL 2WIRE SER 8-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX517BESA+

• Settling Time: 6µs
• Number Of Bits: 8
• Data Interface: I²C, Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 696mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
Typical values are T
TIMING CHARACTERISTICS
(V
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
Note 1: For the MAX518 (full-scale = V
Note 2: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.
Note 3: Input capacitance is code dependent. The highest input capacitance occurs at code FF hex.
Note 4: V REF_ = 4V
Note 5: V REF_ = 4Vp-p, 10kHz, DAC code = 00 hex.
Note 6: Guaranteed by design.
Note 7: I
Note 8: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
Note 9: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
Note 10: Cb = total capacitance of one bus line in pF. t
Note 11: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
4
POWER REQUIREMENTS
Digital-Analog Glitch Impulse
Signal to Noise + Distortion
Ratio (MAX517, MAX519)
Multiplying Bandwidth
(MAX517, MAX519)
Wideband Amplifier Noise
Supply Voltage
Supply Current
Serial Clock Frequency
Bus Free Time Between a STOP and a
START Condition
Hold Time, (Repeated) Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated START Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL Signals, Receiving
Fall Time of Both SDA and SCL Signals, Receiving
Fall Time of SDA Transmitting
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
DD
DD
_______________________________________________________________________________________
= 5V ±10%, V
= 5V ±10%, T
PARAMETER
output swing when loaded with 10kΩ to GND.
code of all other DACs to 00 hex.
bridge the undefined region of SCL’s falling edge.
2
C compatible mode. R
A
REF_
PARAMETER
A
= T
P-P
= +25°C.)
= 4V (MAX517, MAX519), R
MIN
, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the
to T
MAX
PULLUP
SYMBOL
SINAD
, unless otherwise noted. Typical values are T
V
I
DD
DD
DD
= 1.7kΩ.
) the last three codes are excluded from the TUE and DNL specifications, due to the limited
Code 128 to 127
V
Code = FF hex
V
Normal mode, output(s)
unloaded, all digital inputs
at 0V or V
Power-down mode
REF_
REF_
L
= 4Vp-p at 1kHz, V
= 4Vp-p, 3dB bandwidth
= 10kΩ, C
SYMBOL
R
t
t
t
t
t
HD, DAT
HD, STA
SU, DAT
SU, STO
SU, STA
DD
t
t
and t
t
f
HIGH
LOW
BUF
SCL
Cb
t
t
SP
t
t
R
F
F
F
measured between 0.3V
L
= 100pF, T
CONDITIONS
(Note 9)
(Note 10)
(Note 10)
I
(Notes 6, 11)
SINK
CONDITIONS
≤ 6mA (Notes 7, 10)
DD
= 5V,
MAX517C
MAX517E/M
MAX518C, MAX519C
MAX518E/M, MAX519E/M
A
= T
A
MIN
= +25°C.)
to T
DD
MAX
and 0.7V
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
, unless otherwise noted.
MIN
100
1.3
0.6
1.3
0.6
0.6
0.6
0
0
0
IL
DD
of the SCL signal) in order to
.
MIN
4.5
TYP
TYP
1.5
1.5
2.5
2.5
12
87
60
1
4
MAX
400
300
300
250
400
0.9
50
MAX UNITS
5.5
3.0
3.5
20
5
6
UNITS
kHz
µV
pF
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
ns
nV-s
MHz
mA
dB
µA
RMS
V