AD5531BRUZ Analog Devices Inc, AD5531BRUZ Datasheet - Page 13

• Manufacturer Part Number: AD5531BRUZ
• Description: IC DAC 14BIT SERIAL IN 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5531BRUZ

• Data Interface: Serial
• Settling Time: 20µs
• Number Of Bits: 14
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 60mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 14bit
• Sampling Rate: 50kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: ± 10.8V To ± 13.2V, ± 13.5V To ± 16.5V
• Supply Current: 2mA
• Digital: RoHS Compliant
• Number Of Channels: 1
• Resolution: 14b
• Conversion Rate: 50KSPS
• Interface Type: SER 3W SPI QSPI UW
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): ±12/±15V
• Architecture: R-2R
• Power Supply Requirement: Dual
• Output Type: Voltage
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): ±10.8V
• Dual Supply Voltage (max): ±16.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
DAC ARCHITECTURE
The AD5530/AD5531 are pin-compatible 12- and 14-bit DACs.
The AD5530 consists of a straight 12-bit R-2R voltage mode
DAC, and the AD5531 consists of a 14-bit R-2R section. Using a
5 V reference connected to the REFIN pin and REFAGND tied
to 0 V, a bipolar ±10 V voltage output results. The DAC coding
is straight binary.
SERIAL INTERFACE
Serial data on the SDIN input is loaded to the input register
under the control of SCLK, SYNC
operation transfers a 16-bit word to the AD5530/AD5531.
Figure 2 and Figure 3 show the timing diagrams. Figure 18 and
Figure 19 show the contents of the input shift register. Twelve or
14 bits of the serial word are data bits; the rest are don’t cares.
The serial word is framed by the signal,
low transition on
register on the falling edges of SCLK. There are two ways the
DAC register and output can be updated. The LDAC signal is
examined on the falling edge of SYNC ; depending on its status,
either a synchronous or asynchronous update is selected. If
LDAC is low, then the DAC register and output are updated on
the low-to-high transition of SYNC . Alternatively, if LDAC is
high upon sampling, the DAC register is not loaded with the
new data on a rising edge of SYNC . The contents of the DAC
register and the output voltage are updated by bringing LDAC
low any time after the 16-bit data transfer is complete. LDAC
can be tied permanently low if required. A simplified diagram
of the input loading circuitry is illustrated in Figure 20.
DB15 (MSB)
DB15 (MSB)
X X
X X
D11
D13
Figure 18. AD5530 Input Shift Register Contents
Figure 19. AD5531 Input Shift Register Contents
D10
D12
D11
D9
SYNC , data is latched into the input shift
D8 D7
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
D6 D5
DATA BITS
, and
D4 D3 D2 D1 D0 X X
LDAC
SYNC
. A write
. After a high-to-
DB0 (LSB)
DB0 (LSB)
Rev. B | Page 13 of 20
Data written to the part via SDIN is available on the SDO pin 16
clocks later if the readback function is not used. SDO data is
clocked out on the falling edge of the serial clock with some delay.
PD FUNCTION
The
mode. While in this mode, power consumption is at a minimum;
the device draws only 50 μA of current. The
not affect the contents of the DAC register.
READBACK FUNCTION
The AD5530/AD5531 allows the data contained in the DAC
register to be read back if required. The pins involved are the
RBEN
the next falling edge of SCLK, the contents of the DAC register
are transferred to the shift register. RBEN can be used to frame
the readback data by leaving it low for 16 clock cycles, or it can
be asserted high after the required hold time. The shift register
contains the DAC register data and this is shifted out on the
SDO line on each falling edge of SCLK with some delay. This
ensures the data on the serial data output pin is valid for the
falling edge of the receiving part. The two MSBs of the 16-bit
word are 0s.
CLR FUNCTION
The falling edge of CLR causes V
potential as DUTGND. The contents of the registers remain
unchanged, so the user can reload the previous data with LDAC
after CLR is asserted high. Alternatively, if LDAC is tied low, the
output is loaded with the contents of the DAC register auto-
matically after CLR is brought high.
PD
and SDO (serial data out). When
pin allows the user to place the device into power-down
REFIN
LDAC
SYNC
SDIN
Figure 20. Simplified Serial Interface
SYNC REGISTER
DAC REGISTER
12-/14-BIT DAC
16-BIT SHIFT
REGISTER
14
14
14
OUT
to be reset to the same
AD5530/AD5531
RBEN
PD function does
OUTPUT
SDO
is taken low, on