AD7391ARZ Analog Devices Inc, AD7391ARZ Datasheet - Page 5
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AD7391ARZ
Manufacturer Part Number
AD7391ARZ
Description
IC DAC 10BIT 3V SRL-IN 8-SOIC
Manufacturer
Analog Devices Inc
Datasheet
1.AD7391ARZ.pdf
(12 pages)
Specifications of AD7391ARZ
Data Interface
Serial, SPI™
Settling Time
70µs
Number Of Bits
10
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
500µW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Resolution (bits)
10bit
Sampling Rate
17kSPS
Input Channel Type
Serial
Supply Voltage Range - Analogue
2.7V To 5.5V
Supply Current
55µA
Digital Ic Case Style
SOIC
Package
8SOIC N
Resolution
10 Bit
Conversion Rate
17 KSPS
Architecture
R-2R
Digital Interface Type
Serial (3-Wire, SPI, QSPI)
Number Of Outputs Per Chip
1
Output Type
Voltage
Full Scale Error
±32 mV
Integral Nonlinearity Error
±2 LSB
Maximum Settling Time
70(Typ) us
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD7391ARZ
Manufacturer:
Analog Devices Inc
Quantity:
135
Part Number:
AD7391ARZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD7391ARZ-REEL
Manufacturer:
AD
Quantity:
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Company:
Part Number:
AD7391ARZ-REEL7
Manufacturer:
AD
Quantity:
2 281
Part Number:
AD7391ARZ-REEL7
Manufacturer:
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Quantity:
20 000
CLK
↑
X
X
X
X
↑ = Positive logic transition.
X = Don’t care.
AD7390
AD7391
V
OUT
CLR
H
H
L
↑
↑
CLK
CLK
CLR
SDI
SDI
LD
LD
FS
ZS
MSB
B11
D11
MSB
B9
D9
Table II. AD7390 Serial Input Register Data Format, Data is Loaded in the MSB-First Format
Table III. AD7391 Serial Input Register Data Format, Data is Loaded in the MSB-First Format
LD
H
L
X
H
L
B10
D10
t
LD1
D11
AD7390
B8
D8
Serial Shift Register Function
Shift-Register-Data Advanced One-Bit
Disables
No Effect
No Effect
Disabled
D10
B9
D9
t
AD7391
LD1
B7
D7
D9
t
CL
t
B8
D8
DS
Table I. Control-Logic Truth Table
B6
D6
t
DH
D7
B7
D7
t
CH
B5
D5
B6
D6
D5
Updated with Current Shift Register Contents
Previous SR Contents Loaded (Avoid usage of CLR
DAC Register Function
Latched
Loaded with all Zeros
Latched with all Zeros
when LD is logic low, since SR data could be corrupted
if a clock edge takes place, while CLR returns high.)
t
B5
D5
B4
D4
LDW
D4
t
S
D3
B4
D4
B3
D3
DAC REGISTER LOAD
D2
ERROR BAND
0.1% FS
B3
D3
D1
B2
D2
B2
D2
AD7390/AD7391
D0
t
CLRW
t
S
t
LD2
B1
D1
B1
D1
LSB
B0
D0
LSB
B0
D0