MAX5104EEE+ Maxim Integrated Products, MAX5104EEE+ Datasheet - Page 3

• Manufacturer Part Number: MAX5104EEE+
• Description: IC DAC 12BIT DUAL SER 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5104EEE+

• Settling Time: 15µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Number Of Dac Outputs: 2
• Resolution: 12 bit
• Interface Type: Serial (SPI)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: - 40 C
• Supply Current: 0.5 mA
• Voltage Reference: 1.4 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
are at T
Note 1: Accuracy is specified from code 6 to code 4095.
Note 2: Accuracy is better than 1LSB for V
Note 3: Digital inputs are set to either V
Note 4: SCLK minimum clock period includes the rise and fall times.
DIGITAL OUTPUTS (DOUT, UPO)
DYNAMIC PERFORMANCE
POWER SUPPLIES
TIMING CHARACTERISTICS
Output High Voltage
Output Low Voltage
Voltage Output Slew Rate
Output Settling Time
Output Voltage Swing
OSA or OSB Input Resistance
Time Required to Exit Shutdown
Digital Feedthrough
Digital Crosstalk
Positive Supply Voltage
Power-Supply Current
Power-Supply Current
in Shutdown
Reference Current in Shutdown
SCLK Clock Period
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall to SCLK Rise
Setup Time
SCLK Rise to CS Rise
Hold Time
SDI Setup Time
SDI Hold Time
SCLK Rise to DOUT
Valid Propagation Delay
SCLK Fall to DOUT
Valid Propagation Delay
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold
CS Pulse Width High
DD
= +5V ±10%, V
A
end points.
= +25°C (OS_ connected to AGND for a gain of +2V/V).)
PARAMETER
Low-Power, Dual, Voltage-Output, 12-Bit DAC
_______________________________________________________________________________________
REFA
= V
REFB
I
SYMBOL
DD(SHDN)
= +2.048V, R
R
t
t
t
t
V
V
t
t
t
V
I
t
t
CSW
t
t
CSS
CSH
t
DO1
DO2
SR
CS0
CS1
OS_
DD
CH
DH
CP
CL
DS
OH
DD
OL
DD
OUT_
or DGND, code = 0000 hex, R
I
I
To 1/2LSB of full-scale, V
Rail-to-rail (Note 2)
CS = V
(Note 3)
(Note 3)
(Note 4)
C
C
SOURCE
SINK
LOAD
LOAD
greater than 6mV and less than V
L
= 10kΩ, C
= 2mA
DD
= 200pF
= 200pF
= 2mA
, SCLK = 100kHz, V
L
CONDITIONS
= 100pF, T
STEP
L
A
= .
SCLK
= 4V
= T
with Serial Interface
MIN
= 5Vp-p
DD
to T
- 50mV. Guaranteed by PSRR test at the
MAX
, unless otherwise noted. Typical values
V
DD
MIN
100
100
4.5
24
40
40
40
40
10
40
0
0
- 0.5
0 to V
TYP
0.13
0.75
0.5
15
34
25
5
5
2
0
DD
MAX
0.40
0.65
5.5
±1
10
80
80
UNITS
V/µs
nVs
nVs
mA
kΩ
µA
µA
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
V
3