AD7398BRUZ Analog Devices Inc, AD7398BRUZ Datasheet - Page 16

• Manufacturer Part Number: AD7398BRUZ
• Description: IC DAC 12BIT QUAD SRL-IN 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7398BRUZ

• Data Interface: Serial
• Settling Time: 6µs
• Number Of Bits: 12
• Number Of Converters: 4
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 16mW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 167kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 1.6mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7398/AD7399
POWER-ON RESET
When the V
strobe forces all the input and DAC registers to the zero-code
state. The V
ramp without drooping in order to have consistent results,
especially in the region of V
has no effect on the power-on reset performance. The DAC
register data stays at zero until a valid serial register data load
takes place.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND) and V
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD7398/AD7399 is via a
serial bus that uses standard protocol compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire interface consisting of a clock signal, a data
signal, and a synchronization signal. The AD7398/AD7399
require a 16-bit/14-bit data word with data valid on the rising edge
of CLK. The DAC update can be done automatically when all the
data is clocked in, or it can be done under control of LDAC .
ADSP-2101 to AD7398/AD7399 Interface
Figure 29 shows a serial interface between the AD7398/AD7399
and the ADSP-2101. The ADSP-2101 is set to operate in the serial
port (SPORT) transmit alternate framing mode. The ADSP-2101 is
programmed through the SPORT control register and should be
configured as follows: Internal clock operation, active low framing,
16-bit-word length. For the AD7398, transmission is initiated by
writing a word to the Tx register after the SPORT has been
enabled. For the AD7399, the first two bits are don’t care as the
AD7399 keeps the last 14 bits. Similarly, transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled. Because of the edge-triggered difference, an inverter is
required at the SCLKs between the DSP and the DAC.
Figure 29. ADSP-2101 to AD7398/AD7399 Interface
DD
1
DD
ADDITIONAL PINS OMITTED FOR CLARITY.
ADSP-2101
Figure 28. Equivalent ESD Protection Circuits
power supply should have a smooth positive
power supply is turned on, an internal reset
SCLK
DIGITAL INPUTS
V
TFS
FO
DT
DD
1
5kΩ
DD
= 1.5 V to 2.2 V. The V
GND
DD
LDAC
CS
SDI
CLK
as shown in Figure 28.
AD7398/
AD7399
SS
supply
Rev. C | Page 16 of 24
68HC11/68L11 to AD7398/AD7399 Interface
Figure 30 shows a serial interface between the AD7398/AD7399
and the 68HC11/68L11 microcontroller. SCK of the 68HC11/
68L11 drives the CLK of the DAC, and the MOSI output drives the
serial data lines SDI. CS signal is driven from one of the port lines.
The 68HC11/68L11 are configured for master mode; MSTR = 1,
CPOL = 0, and CPHA = 0. Data appearing on the MOSI output is
valid on the rising edge of SCK.
MICROWIRE™ to AD7398/AD7399 Interface
Figure 31 shows an interface between the AD7398/AD7399 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and into the AD7398/
AD7399 on the rising edge of the serial clock. No glue logic is
required as the DAC clocks data into the input shift register on
the rising edge.
80C51/80L51 to AD7398/AD7399 Interface
A serial interface between the AD7398/AD7399 and the 80C51/
80L51 microcontroller is shown in Figure 32. TxD of the micro-
controller drives the CLK of the AD7398/AD7399, and RxD drives
the serial data line of the DAC. P3.3 is a bit-programmable pin on
the serial port that is used to drive CS .
Figure 30. 68HC11/68L11 to AD7398/AD7399 Interface
Figure 32. 80C51/80L51 to AD7398/AD7399 Interface
Figure 31. MICROWIRE to AD7398/AD7399 Interface
1
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
MICROWIRE
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDITIONAL PINS OMITTED FOR CLARITY.
68HC11/
68L11
80C51/
80L51
MOS1
SCK
SCK
P3.4
P3.3
RxD
PC6
PC7
TxD
1
1
CS
SO
1
LDAC
CS
SDI
CLK
CS
SDI
CLK
LDAC
CS
SDI
CLK
AD7398/
AD7398/
AD7398/
AD7399
AD7399
AD7399