AD5327BRUZ Analog Devices Inc, AD5327BRUZ Datasheet - Page 19

• Manufacturer Part Number: AD5327BRUZ
• Description: IC DAC 12BIT QUAD 2.5V 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5327BRUZ

• Data Interface: Serial
• Settling Time: 8µs
• Number Of Bits: 12
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 4.5mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 125kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.5V To 5.5V
• Supply Current: 500µA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The time to exit power-down is typically 2.5 μs for V
and 5 μs when V
of PD to when the output voltage deviates from its power-down
voltage. See Figure 23 for a plot.
MICROPROCESSOR INTERFACING
ADSP-2101/ADSP-2103-to-
AD5307/AD5317/AD5327 Interface
Figure 37 shows a serial interface between the AD5307/AD5317/
AD5327 and the ADSP-2101/ADSP-2103. The ADSP-2101/
ADSP-2103 should be set up to operate in the SPORT transmit
alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is
programmed through the SPORT control register and should be
configured as follows: internal clock operation, active low framing,
16-bit word length. Transmission is initiated by writing a word
to the Tx register after SPORT is enabled. The data is clocked
out on each rising edge of the DSP’s serial clock and clocked
into the AD5307/AD5317/AD5327 on the falling edge of the
DAC’s SCLK.
68HC11/68L11-to-AD5307/AD5317/AD5327 Interface
Figure 38 shows a serial interface between the AD5307/AD5317/
AD5327 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5307/AD5317/
AD5327, and the MOSI output drives the serial data line (DIN)
of the DAC. The SYNC signal is derived from a port line (PC7).
The set-up conditions for correct operation of this interface are as
follows: The 68HC11/68L11 should be configured so that its CPOL
bit is 0 and its CPHA bit is 1. When data is being transmitted to the
DAC, the SYNC line is taken low (PC7). With this configuration,
data appearing on the MOSI output is valid on the falling edge
of SCK. Serial data from the 68HC11/68L11 is transmitted in
8-bit bytes, with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. To load data to
the AD5307/AD5317/AD5327, PC7 is left low after the first
eight bits are transferred and a second serial write operation
is performed to the DAC. PC7 is taken high at the end of this
procedure.
Figure 37. ADSP-2101/ADSP-2103-to-AD5307/AD5317/AD5327 Interface
1
ADDITIONAL PINS OMITTED FOR CLARITY.
STRING DAC
RESISTOR
ADSP-2101/
ADSP-2103
Figure 36. Output Stage During Power-Down
DD
SCLK
TFS
= 3 V. This is the time from the rising edge
DT
1
AMPLIFIER
POWER-DOWN
SYNC
DIN
SCLK
CIRCUITRY
AD5327
AD5307/
AD5317/
1
V
DD
OUT
= 5 V
Rev. C | Page 19 of 28
80C51/80L51-to-AD5307/AD5317/AD5327 Interface
Figure 39 shows a serial interface between the AD5307/AD5317/
AD5327 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
of the AD5307/AD5317/AD5327, and RxD drives the serial data
line of the part. The SYNC signal is again derived from a bit-
programmable pin on the port. In this case, Port Line P3.3 is
used. When data is to be transmitted to the AD5307/AD5317/
AD5327, P3.3 is taken low. The 80C51/80L51 transmits data only
in 8-bit bytes; therefore, only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is left low after
the first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 outputs
the serial data LSB first. The AD5307/AD5317/AD5327 require
their data with the MSB as the first bit received. The
80C51/80L51 transmit routine should take this into account.
MICROWIRE-to-AD5307/AD5317/AD5327 Interface
Figure 40 shows an interface between the AD5307/AD5317/
AD5327 and a MICROWIRE-compatible device. Serial data is
shifted out on the falling edge of the serial clock, SK, and is
clocked into the AD5307/AD5317/AD5327 on the rising edge
of SK, which corresponds to the falling edge of the DAC’s SCLK.
Figure 38. 68HC11/68L11-to-AD5307/AD5317/AD5327 Interface
Figure 39. 80C51/80L51-to-AD5307/AD5317/AD5327 Interface
Figure 40. MICROWIRE-to-AD5307/AD5317/AD5327 Interface
1
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDITIONAL PINS OMITTED FOR CLARITY.
68HC11/68L11
80C51/80L51
MICROWIRE
MOSI
SCK
PC7
P3.3
RxD
TxD
CS
SK
SO
1
1
1
AD5307/AD5317/AD5327
SYNC
SCLK
DIN
SYNC
SCLK
DIN
SYNC
SCLK
DIN
AD5307/
AD5317/
AD5327
AD5327
AD5327
AD5307/
AD5317/
AD5307/
AD5317/
1
1
1