ASEMDLC-LR Abracon Corporation, ASEMDLC-LR Datasheet

ASEMDLC-LR

Manufacturer Part Number

ASEMDLC-LR

Description

Tight Stab.Ind. Temp 3rd Gen. High Perf. Low Jitter LVDS Or CMOS Configurable Dual Output MEMS Oscillator, 10MHZ460MHZ 25ppm -40+85C Temp. Stabilty, 3.2 X 2.5 Mm, 2.25 3.6 Vdc

Manufacturer

Abracon Corporation

Series

ASEMDLCr

Datasheet

1.ASEMDLC-LR.pdf (5 pages)

Specifications of ASEMDLC-LR

Frequency Range

10MHz To 170MHz

Supply Voltage

2.25V To 3.6V

Oscillator Mounting

SMD

No. Of Pins

Operating Temperature Range

-40Â°C To +85Â°C

Rohs Compliant

Yes

Product

MEMS

Package / Case

3.2 mm x 2.5 mm

Frequency

75 MHz to 100 MHz

Frequency Stability

+/- 25 PPM

Termination Style

SMD/SMT

Minimum Operating Temperature

- 40 C

Maximum Operating Temperature

+ 85 C

Output Format

LVDS-CMOS

Dimensions

2.5 mm W x 3.2 mm L

Height

0.85 mm

Mounting Style

SMD/SMT

Lead Free Status / Rohs Status

Details

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LOW JITTER PIN CONFIGURABLE LVDS-CMOS DUAL OUTPUT

STANDARD SPECIFICATIONS:

• Ultra Miniature Pure Silicon

• Pin Configurable LVDS-CMOS Dual output

• Low Jitter (Period Jitter RMS 3ps typical)

• Low Integrated Phase Jitter 2ps max

• Tight Stability +/-10ppm -40 to +85C

• Excellent Shock & Vibration Immunity

FEATURES:

ABRACON IS

ISO9001:2008

CE RTIFIED

Pre-programmed Output Frequency Configuration

Frequency select bits

frequency highlighted in Bold. If other frequency combinations are required, please contact Abracon for customized configuration. Please see the

configurable frequency range in the section 2.0

Key Electrical Specifications

*1. Frequency stability includes frequency variations due to initial tolerance, temp. and power supply voltage

ASEMDLC

Configurable frequency range

Operating Temperature

Storage Temperature

Overall Frequency Stability

Supply Voltage (Vdd)

Startup Time

Enable Time

Disable Time

Disable Current

Tri-state Function (Standby/Disable)

Aging

Supply Current (I

CE RTIFIED

Configuration 1

ULTRA MINIATURE PURE SILICON

Ordering Info

Configuration

Frequency

Custom

Parameters

[FS2, FS1, FS0]

)

OUT2

Freq (MHz)

OUT1

Clock Oscillator

(CMOS)

OUT1

(LVDS)

are weakly tied high so if left floated, the default setting will be [111] and the device will output the associated

LVDS

CMOS

74.25

000

"1" (VIH≥0.75*Vdd) or Open: Oscillation

"0" (VIL<0.25*Vdd) : Hi Z

Minimum

+2.25

-----

-5.0

-20

-55

-50

33.333

74.25

001

Freq Select Bits [FS2, FS1, FS0] – Default is [111]

Contact Abracon for customized configurations

156.25

Typical

• Consumer Electronics

• Storage Area Networks

• SATA, SAS, Fibre Channel

• Passive Optical Networks

• EPON, 10G-EPON, GPON, 10G-PON

• Ethernet

• 1G, 10GBASE-T/KR/LR/SR, and FCoE

• HD/SD/SDI Video & Surveillance

• PCI Express

010

125

-----

APPLICATIONS:

CLOCK OSCILLATOR

303 3 2 Esp e r anza , Ra n c h o San t a M a r g a r i t a , Calif o r ni a 926 8 8

t e l 949-546-800 0

Visit

011

150

125

www.abracon.com

Maximum

+150

+3.6

+5.0

-----

+70

+50

460

170

100

125

for Terms & Conditions of Sale

f a x 949-546-80 0 1

Units

MHz

ppm

RoHS

°C

Compliant

101

125

Commercial,

Industrial temp range

See options

40kΩ pull-up resistor

embedded

First year

LVDS output: RL=100Ω,

F01=125MHz

CMOS output: CL=15pF,

F02=75MHz

LVDS-CMOS Dual Output

110

100

ASEMDLC

Notes

| w w w . a b r a c on.c o m

Pin Con gurable

Life Siz e

3.2 x 2.5 x 0.85 mm

Revised: 03.25.11

Technology!

Low Jitter

3G MEMS

| | | | | | | | | | | | | |

MEMS

111

100

Related parts for ASEMDLC-LR

ASEMDLC-LR Summary of contents

Page 1

... Open: Oscillation "0" (VIL<0.25*Vdd -5.0 ----- ----- 49 Visit 303 3 2 Esp e r anza , San Calif 926 949-546-800 0 ASEMDLC RoHS Pb Compliant Pin Con gurable LVDS-CMOS Dual Output 011 100 101 110 150 125 125 100 125 ...

Page 2

... Visit 303 3 2 Esp e r anza , San Calif 926 949-546-800 0 ASEMDLC RoHS Pb Compliant 1.40 V RL=100 Ω, Differential 50 mV ----- mV Single-Ended ----- ps RL=50 Ω, CL=2pF ----- ps 20%/80%*VDD 52 % Differential ...

Page 3

... APPLICATIONS: Minimum Maximum -0.3 +4.0 -0.3 V +0.3 dd ----- +150 -55 +150 ----- +260 4,000 400 1,500 ASEMDLC - - - Overall Freq. Stability Blank: ±50ppm Y: ±10ppm R: ±25 ppm Freq Select Bits [FS2, FS1, FS0] – Default is [111] 000 001 010 011 74.25 74.25 156.25 150 27 33.333 125 ...

Page 4

... Power Supply 2 for CMOS Output Power Power Supply I Most significant bit for output drive strength selection for CMOS Visit www.abracon.com 303 3 2 Esp e r anza , San Calif 926 949-546-800 0 ASEMDLC RoHS Life Siz e Pb 3.2 x 2.5 x 0.85 mm Compliant | | | | | | | | | | | | | | Revised: 03.25.11 for Terms & Conditions of Sale ...

Page 5

... Abracon Corporation is required. Please contact Abracon Corporation for more information. ABRACON IS ABRACON IS ISO9001:2008 CE RTIFIED CE RTIFIED CE RTIFIED CLOCK OSCILLATOR TM RoHS Pb Compliant APPLICATIONS: Unit orientation in tube: Visit www.abracon.com for Terms & Conditions of Sale 303 3 2 Esp e r anza , San Calif 926 949-546-800 949-546- ASEMDLC Life Siz e 3.2 x 2 Revised: 03.25. on ...

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