AD5328ARUZ Analog Devices Inc, AD5328ARUZ Datasheet - Page 6

• Manufacturer Part Number: AD5328ARUZ
• Description: IC DAC 12BIT OCTAL W/BUF 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5328ARUZ

• Data Interface: Serial
• Settling Time: 6µs
• Number Of Bits: 12
• Number Of Converters: 8
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 4.5mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 167kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.5V To 5.5V
• Supply Current: 1mA
• Digital Ic Case Style: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5308/AD5318/AD5328
Table 3. Timing Characteristics
Parameter
t
t
t
t
t
t
t
t
t
t
t
1
2
3
1
2
3
4
5
6
7
8
9
10
11
Guaranteed by design and characterization; not production tested.
All input signals are specified with t
See Figure 2
.
LDAC
LDAC
SYNC
SCLK
DIN
1
2
NOTES
1
2
A, B Version
Limit at T
33
13
13
13
15
5
4.5
0
50
20
20
0
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
t
8
R
= t
MIN
1, 2, 3
F
= 5 ns (10% to 90% of V
, T
DB15
MAX
t
t
6
4
t
5
t
3
Figure 2. Serial Interface Timing Diagram
DD
) and timed from a voltage level of (V
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t
1
t
2
Rev. F | Page 6 of 28
DB0
t
t
7
11
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time; temperature range (A, B
verstion): −40°C to +105°C
SYNC to SCLK falling edge setup time; temperature range (A, B
verstion): −40°C to +125°C
Data set up time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
LDAC pulse width
SCLK falling edge to LDAC rising edge
SCLK falling edge to LDAC falling edge
t
9
t
10
IL
+ V
IH
)/2.