AD7545AKNZ Analog Devices Inc, AD7545AKNZ Datasheet - Page 6

• Manufacturer Part Number: AD7545AKNZ
• Description: IC DAC 12BIT MULTIPLYING 20-DIP
• Manufacturer: Analog Devices Inc

Specifications of AD7545AKNZ

• Data Interface: Parallel
• Settling Time: 2µs
• Number Of Bits: 12
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Resolution (bits): 12bit
• Input Channel Type: Parallel
• Supply Current: 2mA
• Digital Ic Case Style: DIP
• No. Of Pins: 20
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

AD7545A
Invalid Data: When WR and CS are both low, the latches are
transparent and the D/A converter inputs follow the data inputs.
In some bus systems, data on the data bus is not always valid for
the whole period during which WR is low, and as a result invalid
data can briefly occur at the D/A converter inputs during a write
cycle. Such invalid data can cause unwanted signals or glitches
at the output of the D/A converter. The solution to this prob-
lem, if it occurs, is to retime the write pulse, WR, so it only
occurs when data is valid.
Digital Glitches: Digital glitches result due to capacitive cou-
pling from the digital lines to the OUT1 and AGND terminals.
This should be minimized by screening the analog pins of the
AD7545A (Pins 1, 2, 19, 20) from the digital pins by a ground
track run between Pins 2 and 3 and between Pins 18 and 19 of
the AD7545A.
Note how the analog pins are at one end (DIP) or side (LCC
and PLCC) of the package and separated from the digital pins
by V
capacitive coupling can also give rise to crosstalk from the digital-
to-analog sections of the AD7545A, particularly in circuits with
high currents and fast rise and fall times. This type of crosstalk is
minimized by using V
be taken to ensure that the +5 V used to power the AD7545A is
free from digitally induced noise.
Temperature Coefficients: The gain temperature coefficient
of the AD7545A has a maximum value of 5 ppm/°C and a typi-
cal value of 2 ppm/°C. This corresponds to worst case gain shifts
of 2 LSBs and 0.8 LSBs respectively over a 100°C temperature
range. When trim resistors R1 and R2 (such as in Figure 4) are
used to adjust full-scale range, the temperature coefficient of R1
and R2 should also be taken into account. The reader is referred
to Analog Devices Application Note “Gain Error and Gain
Temperature Coefficient to CMOS Multiplying DACs,” Publi-
cation Number E630c–5–3/86.
SINGLE SUPPLY OPERATION
The ladder termination resistor of the AD7545A (Figure 1) is
connected to AGND. This arrangement is particularly suitable
for single supply operation because OUT1 and AGND may be
biased at any voltage between DGND and V
AGND should never go more than 0.3 volts less than DGND or
an internal diode will be turned on and a heavy current may
flow that will damage the device. (The AD7545A is, however,
protected from the SCR latchup phenomenon prevalent in many
CMOS devices.)
Figure 7 shows the AD7545A connected in a voltage switching
mode. OUT1 is connected to the reference voltage and AGND
is connected to DGND. The D/A converter output voltage is
available at the V
equal to R. R
OUT1 to minimize stray capacitance effects.
Figure 7. Single Supply Operation Using Voltage Switch-
ing Mode
DD
and DGND to aid screening at the board level. On-chip
FB
is not used in this circuit and should be tied to
REF
pin and has a constant output impedance
DD
= +5 volts. However, great care should
DD
. OUT1 and
–6–
The loading on the reference voltage source is code-dependent
and the response time of the circuit is often determined by the
behavior of the reference voltage with changing load conditions.
To maintain linearity, the voltages at OUT1 and AGND should
remain within 2.5 volts of each other, for a V
V
OUT1 and AGND is increased to more than 2.5 V, the differ-
ential nonlinearity of the DAC will increase and the linearity of
the DAC will be degraded. Figures 8 and 9 show typical curves
illustrating this effect for various values of reference voltage and
V
by some value, then OUT1 and AGND may be biased up. The
effect on linearity and differential nonlinearity will be the same
as reducing V
Figure 8. Differential Nonlinearity vs. V
Circuit. Reference Voltage = 2.5 Volts. Shaded Area Shows
Range of Values of Differential Nonlinearity that Typically
Occur for all Grades.
Figure 9. Differential Nonlinearity vs. Reference Voltage
for Figure 7 Circuit. V
Range of Values of Differential Nonlinearity that Typically
Occur for all Grades.
DD
DD
. If the output voltage is required to be offset from ground
is reduced from 15 V, or the differential voltage between
DD
by the amount of the offset.
DD
= 15 Volts. Shaded Area Shows
DD
DD
for Figure 7
of 15 volts. If
REV. C