CS4382A-CQZ Cirrus Logic Inc, CS4382A-CQZ Datasheet - Page 30

• Manufacturer Part Number: CS4382A-CQZ
• Description: IC DAC 8CH 114DB 192KHZ 48LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4382A-CQZ

• Package / Case: 48-LQFP
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 680mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 5 V
• Operating Temperature Range: + 85 C
• Maximum Power Dissipation: 390 mW
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1524 - BOARD EVAL FOR CS4382A DAC
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1061

30
4.14.3 SPI Mode
4.14.3.1 SPI Write
To write to the device, follow the procedure below while adhering to the Control Port Switching Specifica-
tions in
1. Bring CS low.
2. The address byte on the CDIN pin must then be 00110000.
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see
6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring
In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial Control Port clock, CCLK
(see
is used to control SPI writes to the Control Port. When the device detects a high-to-low transition on the
AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
instructions followed by step 1 of the I²C Read section. If no further reads from other registers are de-
sired, initiate a STOP condition to the bus.
are written, then bring CS high.
CS high, and follow the procedure detailed from step 1. If no further writes to other registers are de-
sired, bring CS high.
Figure 18
Section
S C L
S D A
N o te : If o p e ra tio n is a w rite , th is b y te c o n ta in s th e M e m o ry A d d re s s P o in te r, M A P .
C S
C C LK
C DIN
for the clock-to-data relationship). There is no AD0 pin. Pin CS is the chip select signal and
S ta rt
2.
0 01 1 00
Section
M A P = M em ory A d dress P oin te r
A D D R E S S
Figure 18. Control Port Timing, SPI Mode
Figure 17. Control Port Timing, I²C Mode
0011000
C H IP
A D D R
AD 0
4.14.1) is set to 1, repeat the previous step until all the desired registers
R /W
R /W
A C K
M A P
D AT A
1-8
N o te 1
M S B
byte 1
A C K
D A TA
D A TA
1-8
byte n
LSB
A C K
S top
CS4362A
DS617F1