CS4385-CQZ Cirrus Logic Inc, CS4385-CQZ Datasheet - Page 26
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CS4385-CQZ
Manufacturer Part Number
CS4385-CQZ
Description
IC DAC 8CH 114DB 192KHZ 48LQFP
Manufacturer
Cirrus Logic Inc
Specifications of CS4385-CQZ
Package / Case
48-LQFP
Number Of Bits
24
Data Interface
Serial
Number Of Converters
8
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
520mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Conversion Rate
216 KSPS
Resolution
24 bit
Interface Type
Serial
Operating Supply Voltage
5 V
Operating Temperature Range
+ 85 C
Maximum Power Dissipation
390 mW
Mounting Style
SMD/SMT
Number Of Dac Outputs
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1154 - BOARD EVAL FOR CS4385 DAC
Settling Time
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1063
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
CS4385-CQZ
Manufacturer:
CIRRUS
Quantity:
638
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CS4385-CQZ
Manufacturer:
CRYSTAL
Quantity:
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Part Number:
CS4385-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
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Part Number:
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26
4.7
4.8
ATAPI Specification
The CS4365 implements the channel-mixing functions of the ATAPI CD-ROM specification. The
ATAPI functions are applied per A-B pair. Refer to
tion.
Direct Stream Digital (DSD) Mode
In Software Mode, the DSD/PCM bits (Reg. 02h) are used to configure the device for DSD Mode. The
DSD_DIF bits (Reg 04h) then control the expected DSD rate and MCLK ratio.
The DIR_DSD bit (Reg 04h) selects between two proprietary methods for DSD-to-analog conversion. The
first method uses a decimation-free DSD processing technique which allows for features such as matched
PCM-level output, DSD volume control, and 50kHz on-chip filter. The second method sends the DSD data
directly to the on-chip switched-capacitor filter for conversion (without the above-mentioned features).
The DSD_PM_EN bit (Reg. 04h) selects Phase Modulation (data plus data inverted) as the style of data
input. In this mode, the DSD_PM_mode bit selects whether a 128Fs or 64x clock is used for phase modu-
lated 64x data (see
the CS4365, but may lower the sensitivity to board-level routing of the DSD data signals.
The CS4365 can detect errors in the DSD data which does not comply with the SACD specification. The
STATIC_DSD and INVALID_DSD bits (Reg. 04h) allow the CS4365 to alter the incoming invalid DSD data.
Depending on the error, the data may either be attenuated or replaced with a muted DSD signal (the
MUTEC pins would be set according to the DAMUTE bit (Reg. 08h)).
More information for any of these register bits can be found in
The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation
index) at full rated performance. Signals of +3 dB-SACD may be applied for brief periods of time, however;
performance at these levels is not guaranteed. If sustained +3 dB-SACD levels are required, the digital vol-
ume control should be set to -3.0 dB. This same volume control register affects PCM output levels. There
is no need to change the volume control setting between PCM and DSD in order to have the 0dB output
levels match (both 0 dBFS and 0 dB-SACD will output at -3 dB in this case).
SDINx
Right Chan nel
Left Chan nel
Audio D ata
Audio D ata
Figure
Figure 17. ATAPI Block Diagram (x = channel pair 1, 2, or 3)
18). Use of Phase Modulation Mode may not directly affect the performance of
Σ
Table 9 on page 42
A Channel
B Channel
Volume
Volume
Control
Control
Section 7. “Filter Plots” on page
and
Σ
Figure 17
for additional informa-
MUTE
MUTE
Aout Ax
AoutBx
CS4365
45.
DS670F2