AD9708ARZ Analog Devices Inc, AD9708ARZ Datasheet
AD9708ARZ
Specifications of AD9708ARZ
Available stocks
Related parts for AD9708ARZ
AD9708ARZ Summary of contents
Page 1
FEATURES Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 8-Bit Resolution Linearity: 1/4 LSB DNL Linearity: 1/4 LSB INL Differential Current Outputs SINAD @ 5 MHz Output Power Dissipation: 175 ...
Page 2
AD9708–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION MONOTONICITY 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) 2 Full-Scale Output Current Output Compliance ...
Page 3
DYNAMIC SPECIFICATIONS P arameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f CLOCK 1 Output Settling Time (t ) (to 0.1%) ST Output Propagation Delay ( Glitch Impulse 1 Output Rise Time (10% to 90%) 1 Output Fall Time ...
Page 4
AD9708 ABSOLUTE MAXIMUM RATINGS* With Parameter Respect to Min AVDD ACOM –0.3 DVDD DCOM –0.3 ACOM DCOM –0.3 AVDD DVDD –6.5 CLOCK, SLEEP DCOM –0.3 Digital Inputs DCOM –0.3 IOUTA, IOUTB ACOM –1.0 COMP1, COMP2 ACOM –0.3 REFIO, FSADJ ACOM ...
Page 5
DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential ...
Page 6
AD9708 Typical AC Characterization Curves Single-Ended Output mA, T OUTA OUTFS A 70 THD @ 50MSPS THD @ 10MSPS 65 THD @ 100MSPS SINAD @ 10MSPS SINAD @ 50MSPS 45 SINAD @ ...
Page 7
FUNCTIONAL DESCRIPTION Figure 12 shows a simplified block diagram of the AD9708. The AD9708 consists of a large PMOS current source array capable of providing total current. The array is divided into 31 equal currents ...
Page 8
AD9708 OPTIONAL EXTERNAL REF BUFFER REFLO +1.2V REF REFIO ADDITIONAL FS ADJ LOAD 0 AD9708 Figure 13. Internal Reference Configuration The internal reference can be disabled by connecting REFLO to AVDD. In this case, an external reference may ...
Page 9
Figure 17 shows a buffered singled-ended output con- figuration in which the op amp, U1, performs an I-V conversion on the AD9708 output current. U1 provides a negative unipolar output voltage and its full-scale output voltage is simply the ...
Page 10
AD9708 – mA OUTFS Figure 19. I vs. I AVDD OUTFS POWER DISSIPATION The power dissipation the AD9708 is ...
Page 11
The necessity and value of this resistor will be dependent upon the logic family used. For a more detailed discussion of the implementation and construction of high speed, mixed signal printed circuit boards, refer to Analog Devices’ ...
Page 12
AD9708 Figure 26. Evaluation Board Schematic –12– REV. B ...
Page 13
REV. B Figure 27. Silkscreen Layer—Top Figure 28. Component Side PCB Layout (Layer 1) –13– AD9708 ...
Page 14
AD9708 Figure 29. Ground Plane PCB Layout (Layer 2) Figure 30. Power Plane PCB Layout (Layer 3) –14– REV. B ...
Page 15
REV. B Figure 31. Solder Side PCB Layout (Layer 4) Figure 32. Silkscreen Layer—Bottom –15– AD9708 ...
Page 16
AD9708 PIN 1 0.0118 (0.30) 0.0040 (0.10) 0.006 (0.15) 0.002 (0.05) SEATING PLANE OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65 ...