CS43L21-CNZ Cirrus Logic Inc, CS43L21-CNZ Datasheet - Page 5

• Manufacturer Part Number: CS43L21-CNZ
• Description: IC DAC 24BIT 98DB 96KHZ 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L21-CNZ

• Package / Case: 32-QFN
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 1.8 V or 2.5 V
• Operating Temperature Range: + 70 C
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1282 - BOARD EVAL FOR CS43L21 DAC
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1187

DS723A1
LIST OF FIGURES
LIST OF TABLES
Figure 1.Typical Connection Diagram (Software Mode) ............................................................................. 9
Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 10
Figure 3.Headphone Output Test Load ..................................................................................................... 15
Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 17
Figure 5.Serial Audio Interface Master Mode Timing ................................................................................ 17
Figure 6.Control Port Timing - I²C ............................................................................................................. 18
Figure 7.Control Port Timing - SPI Format ................................................................................................ 19
Figure 8.Output Architecture ..................................................................................................................... 24
Figure 9.De-Emphasis Curve .................................................................................................................... 25
Figure 10.Beep Configuration Options ...................................................................................................... 26
Figure 11.Peak Detect & Limiter ............................................................................................................... 27
Figure 12.Master Mode Timing ................................................................................................................. 29
Figure 13.Tri-State SCLK/LRCK ............................................................................................................... 30
Figure 14.I²S Format ................................................................................................................................. 30
Figure 15.Left-Justified Format ................................................................................................................. 31
Figure 16.Right-Justified Format (DAC only) ............................................................................................ 31
Figure 17.Initialization Flow Chart ............................................................................................................. 32
Figure 18.Control Port Timing in SPI Mode .............................................................................................. 33
Figure 19.Control Port Timing, I²C Write ................................................................................................... 34
Figure 20.Control Port Timing, I²C Read ................................................................................................... 34
Figure 21.THD+N vs. Output Power per Channel at 1.8 V (16 Ω load) .................................................... 54
Figure 22.THD+N vs. Output Power per Channel at 2.5 V (16 Ω load) .................................................... 54
Figure 23.THD+N vs. Output Power per Channel at 1.8 V (32 Ω load) .................................................... 55
Figure 24.THD+N vs. Output Power per Channel at 2.5 V (32 Ω load) .................................................... 55
Figure 25.Power Dissipation vs. Output Power into Stereo 16 Ω ......................................................................56
Figure 26.Power Dissipation vs. Output Power into Stereo 16 Ω (Log Detail) .......................................... 56
Figure 27.Passband Ripple ....................................................................................................................... 60
Figure 28.Stopband ................................................................................................................................... 60
Figure 29.Transition Band ......................................................................................................................... 60
Figure 30.Transition Band (Detail) ............................................................................................................ 60
Table 1. I/O Power Rails ............................................................................................................................. 8
Table 2. Hardware Mode Feature Summary ............................................................................................. 23
Table 3. MCLK/LRCK Ratios .................................................................................................................... 29
CS43L21
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