AD5443YRMZ Analog Devices Inc, AD5443YRMZ Datasheet - Page 21

• Manufacturer Part Number: AD5443YRMZ
• Description: IC DAC 12BIT SERIAL IOUT 10-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5443YRMZ

• Data Interface: Serial
• Design Resources: Unipolar, Precision DC Digital-to-Analog Conversion Using AD5426/32/43 8-Bit to12-Bit DACs (CN0034) Precision, Bipolar Configuration for the AD5426/32/43 8-Bit to12-Bit DACs (CN0036) AC Signal Processing Using AD5426/32/43 Current Output DACs (CN0037) Programmable Gain Element Using AD5426/32/43 Current Output DACs (CN0038) Single-Ended-to-Differential Converters for Voltage Output and Current Output DACs Using AD8042 (CN0143)
• Number Of Bits: 12
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Power Dissipation (max): 25µW
• Settling Time: 50ns
• Resolution (bits): 12bit
• Sampling Rate: 2.5MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 3V To 5.5V
• Supply Current: 400nA
• Digital Ic Case Style: SOP
• Number Of Channels: 1
• Resolution: 12b
• Interface Type: SER 3W SPI QSPI UW
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: R-2R
• Power Supply Requirement: Single
• Output Type: Current
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD5443-DBRDZ - BOARD EVAL CARD CLINUX/STAMP
• Lead Free Status / Rohs Status: Compliant

Standalone Mode
After power-on, write 1001 to the control word to disable daisy-
chain mode. The first falling edge of SYNC resets a counter that
counts the number of serial clocks, ensuring the correct number
of bits are shifted in and out of the serial shift registers. A rising
edge on SYNC during a write causes the write cycle to be aborted.
After the falling edge of the 16th SCLK pulse, data is auto-
matically transferred from the input shift register to the DAC.
For another serial transfer to take place, the counter must be
reset by the falling edge of SYNC .
MICROPROCESSOR INTERFACE
Microprocessor interfacing to this family of DACs is via a serial
bus that uses standard protocol compatible with microcontrollers
and DSP processors. The communications channel is a 3-wire
interface consisting of a clock signal, a data signal, and a
synchronization signal. The devices require a 16-bit word with a
data valid default on the falling edge of SCLK, but this is
changeable via the control bits in the data-word.
ADSP-21xx to AD5426/AD5432/AD5443 Interface
The ADSP-21xx family of DSPs are easily interfaced to this
family of DACs without extra glue logic. Figure 51 shows an
example of an SPI interface between the DAC and the
ADSP-2191M. SCK of the DSP drives the serial data line, DIN.
SYNC is driven from one of the port lines, in this case SPIxSEL .
A serial interface between the DAC and DSP channel
synchronous serial port (SPORT) is shown in Figure 52. In this
interface example, SPORT0 is used to transfer data to the DAC
shift register. Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled. In a write
sequence, data is clocked out on each rising edge of the DSP’s
serial clock and clocked into the DAC input shift register on the
falling edge of its SCLK. The update of the DAC output takes
place on the rising edge of the SYNC signal.
Communication between two devices at a given clock speed is
possible when the following specifications are compatible:
frame sync delay and frame sync setup and hold, data delay and
data setup and hold, and SCLK width. The DAC interface
expects a t4 ( SYNC falling edge to SCLK falling edge setup
time) of 13 ns minimum. Consult the ADSP-21xx user manual
for information on clock and frame sync frequencies for the
SPORT register.
ADDITIONAL PINS OMITTED FOR CLARITY.
ADSP-2191
Figure 51. ADSP-2191 SPI-to-AD5426/AD5432/AD5443 Interface
SPIxSEL
MOSI
SCK
Table 11
shows the SPORT control register.
SYNC
SDIN
SCLK
AD5426/
AD5432/
AD5443
Rev. C | Page 21 of 28
Table 11. SPORT Control Register Setup
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
ITFS
SLEN
ADSP-BF5x to AD5426/AD5432/AD5443 Interface
The ADSP-BF5xx family of processors has an SPI-compatible
port that enables the processor to communicate with SPI-
compatible devices. A serial interface between the ADSP-BF5xx
and the AD526/AD5432/AD5443 DAC is shown in Figure 53.
In this configuration, data is transferred through the master
output/slave input (MOSI) pin. SYNC is driven by the SPI chip
select pin, which is a reconfigured programmable flag pin.
The ADSP-BF5xx processor incorporates the SPORT. A serial
interface between the DAC and the DSP SPORT is shown in
Figure 54. When the SPORT is enabled, initiate transmission by
writing a word to the Tx register. The data is clocked out on
each rising edge of the DSP’s serial clock and clocked into the
DAC’s input shift register on the falling edge of its SCLK. The
DAC output is updated by using the transmit frame synchro-
nization (TFS) line to provide a SYNC signal.
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDITIONAL PINS OMITTED FOR CLARITY.
ADSP-2101/
ADSP-2103/
ADSP-2191
ADSP-BF5xx
ADSP-BF5xx
Figure 53. ADSP-BF5xx-to-AD5426/AD5432/AD5443 Interface
Figure 54. ADSP-BF5xx-to-AD5426/AD5432/AD5443 Interface
Figure 52. ADSP-2101/ADSP-2103/ADSP-2191 SPORT to
SPIxSEL
Setting
1
1
1
1
1
1111
SCLK
SCLK
00
MOSI
SCK
TFS
TFS
DT
DT
AD5426/AD5432/AD5443 Interface
AD5426/AD5432/AD5443
Description
Alternate framing
Active low frame signal
Right-justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
SYNC
SDIN
SCLK
SYNC
SDIN
SCLK
SYNC
SDIN
SCLK
AD5444
AD5444
AD5426/
AD5432/
AD5443