X9241UV Intersil, X9241UV Datasheet - Page 3

• Manufacturer Part Number: X9241UV
• Description: IC DCP QUAD 50K 64TP 20TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9241UV

• Taps: 64
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 30 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Resistance In Ohms: 50K, 50K, 50K, 50K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

X9241
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data. See Figure 7.
The X9241 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command
byte. If the command is followed by a data byte the
X9241 will respond with a final acknowledge.
Array Description
The X9241 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical poten-
tiometer (V
At both ends of each array and between each resistor
segment is a FET switch connected to the wiper (V
output. Within each individual array only one switch may
be turned on at a time. These switches are controlled by
the Wiper Counter Register (WCR). The six least signifi-
cant bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type
identifier (refer to Figure 1 below). For the X9241 this is
fixed as 0101[B].
Figure 1. Slave Address
0
DEVICE TYPE
H
IDENTIFIER
1
and V
0
L
inputs).
1
A3
DEVICE ADDRESS
A2
A1
3864 FHD F08
A0
W
)
3
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs. The X9241 compares the
serial data stream with the address input state; a suc-
cessful compare of all four address bits is required for
the X9241 to respond with an acknowledge.
Acknowledge Polling
The disabling of the inputs, during the internal non-
volatile write operation, can be used to take advantage
of the typical 5ms E
stop condition is issued to indicate the end of the
nonvolatile write command the X9241 initiates the inter-
nal write cycle. ACK polling can be initiated immediately.
This involves issuing the start condition followed by the
device slave address. If the X9241 is still busy with the
write operation no ACK will be returned. If the X9241 has
completed the write operation an ACK will be returned
and the master can then proceed with the next
operation.
Flow 1. ACK Polling Sequence
COMMAND COMPLETED
NONVOLATILE WRITE
ENTER ACK POLLING
INSTRUCTION
ISSUE SLAVE
OPERATION?
RETURNED?
ADDRESS
PROCEED
FURTHER
START
ISSUE
ISSUE
ACK
YES
YES
2
PROM write cycle time. Once the
NO
NO
ISSUE STOP
ISSUE STOP
PROCEED
3864 ILL F01