AD5247BKS100-RL7 Analog Devices Inc, AD5247BKS100-RL7 Datasheet - Page 16

• Manufacturer Part Number: AD5247BKS100-RL7
• Description: IC DGTL POT 128POS SC70-6 T/R
• Manufacturer: Analog Devices Inc

Specifications of AD5247BKS100-RL7

• Rohs Status: RoHS non-compliant
• Taps: 128
• Resistance (ohms): 100K
• Number Of Circuits: 1
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SC-70-6, SC-88, SOT-363
• Resistance In Ohms: 100K
• Number Of Elements: 1
• # Of Taps: 128
• Resistance (max): 100KOhm
• Power Supply Requirement: Single
• Interface Type: Serial (2-Wire/I2C)
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 6
• For Use With: AD5247EVAL - BOARD EVAL FOR AD5247
• Lead Free Status / RoHS Status: Not Compliant

AD5247
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems can be operated at one voltage, a
new component can be optimized at another voltage. When
two systems operate the same signal at two different voltages,
proper level shifting is needed. For instance, users can employ
a 3.3 V E
level shifting scheme is needed to enable a bidirectional commu-
nication so that the setting of the digital potentiometer can be
stored in and retrieved from the E
of the level-shifting implementations. M1 and M2 can be any
N-channel signal FETs, or if V
can be low threshold FETs such as the FDV301N.
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures as shown in Figure 37. This applies
to digital input pins (SDA and SCL).
TERMINAL VOLTAGE OPERATING RANGE
The AD5247 V
conditions for proper 3-terminal digital potentiometer operation.
Supply signals present on Terminal A and Terminal W that exceed
V
(see Figure 38).
DD
V
SDA1
SCL1
DD1
or GND are clamped by the internal forward biased diodes
Figure 36. Level-Shifting for Operation at Different Potentials
Figure 38. Maximum Terminal Voltages Set by V
= 3.3V
2
PROM to interface with a 5 V digital potentiometer. A
E
2
3.3V
PROM
R
DD
Figure 37. ESD Protection of Digital Pins
P
and GND power supply defines the boundary
SDA/
SCL
R
P
S
G
M1
340Ω
D
DD
GND
S
falls below 2.5 V, M1 and M2
G
M2
2
PROM. Figure 36 shows one
LOGIC
D
R
P
AD5247
R
P
5V
V
DD
DD2 =
V
A
W
GND
DD
and GND
5V
SDA2
SCL2
Rev. B | Page 16 of 20
MAXIMUM OPERATING CURRENT
At low code values, the user should be aware that, due to low
resistance values, the current through the RDAC might exceed
the 5 mA limit. In Figure 39, a 5 V supply is placed on the wiper,
and the current through Terminal W and Terminal B is plotted
with respect to code. A line is also drawn denoting the 5 mA
current limit. Note that at low code values (particularly for the
5 kΩ and 10 kΩ options), the current level increases signifi-
cantly. Care should be taken to limit the current flow between
W and B in this state to a maximum continuous current of
5 mA and a maximum pulse current of no more than 20 mA.
Otherwise, degradation or possible destruction of the internal
switch contacts can occur.
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A and Terminal W (see Figure 38), it is important
to power V
and Terminal W; otherwise, the diode is forward-biased such
that V
user’s circuit. The ideal power-up sequence is in the following
order: GND, V
of powering V
as long as they are powered after V
DD
0.01
100
0.1
10
is powered unintentionally and can affect the rest of the
1
0
DD
/GND before applying any voltage to Terminal A
A
DD
Figure 39. Maximum Operating Current
16
and V
, digital inputs, V
32
W
and the digital inputs is not important
5mA CURRENT LIMIT
48
CODE (Decimal)
64
A
DD
, and V
/GND.
R
AB
80
= 10kΩ
R
AB
W
. The relative order
= 100kΩ
96
R
R
AB
AB
= 5kΩ
= 50kΩ
112
128