AD5222BR10 Analog Devices Inc, AD5222BR10 Datasheet - Page 7

• Manufacturer Part Number: AD5222BR10
• Description: IC DGTL POT DUAL 128POS 14-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD5222BR10

• Rohs Status: RoHS non-compliant
• Taps: 128
• Resistance (ohms): 10K
• Number Of Circuits: 2
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Volatile
• Interface: Up/Down Counter
• Voltage - Supply: 2.7 V ~ 5.5 V, ±2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Resistance In Ohms: 10K
• Number Of Elements: 2
• # Of Taps: 128
• Resistance (max): 10KOhm
• Power Supply Requirement: Single/Dual
• Interface Type: Increment-Decrement
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): ±2.5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): ±2.3V
• Dual Supply Voltage (max): ±2.7V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / Rohs Status: Not Compliant

REV. 0
Figure 21. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
Figure 22. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
Figure 24. Power Supply Sensitivity Test Circuit (PSS,
PSRR)
V+
~
V
MS2
Figure 23. Wiper Resistance Test Circuit
V
DD
V
A
A
B
V+
W
NO CONNECT
A
B
DUT
W
A
DUT
B
A
DUT
B
V
W
W
W
V
I
W
V
MS1
MS
=
V
DD
V+ = V
V
PSRR (dB) = 20 LOG
PSS (%/%) = –––––––
V+ = V
1LSB = V+/128
/R
MS
NOMINAL
R
V
W
MS
I
W
DD
DD
= [V
± 10%
MS1
– V
V
V
MS
DD
MS2
%
%
(
]/I
–––––
W
V
V
MS
DD
)
–7–
Figure 26. Noninverting Programmable Gain Test Circuit
Figure 25. Inverting Programmable Gain Test Circuit
Figure 28. Incremental ON Resistance Test Circuit
Figure 27. Gain vs. Frequency Test Circuit
Parametric Test Circuits–AD5222
V
IN
DUT
B
V
A
V
IN
IN
W
DUT
A
DUT
I
SW
DUT
B
W
W
R
CODE = 00
A
B
SW
OP279
+
B
W
+5V
OP279
–5V
=
0.1V
I
+5V
–5V
OP42
SW
+15V
–15V
H
0 TO V
0.1V
V
OUT
DD
V
OUT
V
OUT