AD5203ARU100 Analog Devices Inc, AD5203ARU100 Datasheet - Page 3

• Manufacturer Part Number: AD5203ARU100
• Description: IC POT DGTL QUAD 64POS 24TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5203ARU100

• Rohs Status: RoHS non-compliant
• Taps: 64
• Resistance (ohms): 100K
• Number Of Circuits: 4
• Temperature Coefficient: 700 ppm/°C Typical
• Memory Type: Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Resistance In Ohms: 100K
• Number Of Elements: 4
• # Of Taps: 64
• Resistance (max): 100KOhm
• Power Supply Requirement: Single
• Interface Type: Serial (3-Wire/SPI)
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Not Compliant

REV. 0
NOTES
10
11
12
13
ABSOLUTE MAXIMUM RATINGS*
(T
V
V
I
Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . –40 C to +85 C
Maximum Junction Temperature (T
Storage Temperature . . . . . . . . . . . . . . . . . . –65 C to +150 C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300 C
Package Power Dissipation . . . . . . . . . . . . . . (T
Thermal Resistance
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
ADDR
B7
A1
MSB
2
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5203 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
1
2
3
4
5
6
7
8
9
AB
Typicals represent average readings at +25 C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
V
INL and DNL are measured at V
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Measured at the AX terminals. All AX terminals are open-circuited in shutdown mode.
Worst case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. See Figure 19 for a plot of I
P
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27 test circuit. I
for both V
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 26 test circuit.
inputs result in minimum power dissipation.
All dynamic characteristics use V
Measured at a V
See timing diagrams for location of measured values. All input control voltages are specified with t
of 1.6 V. Switching characteristics are measured using both V
Propagation delay depends on value of V
7
DD
A
DISS
AB
A
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 C/W
TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 C/W
, V
, I
= +25 C, unless otherwise noted)
= V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
AW
is calculated from (I
B
, V
DD
, I
B6
A0
LSB
2
DD
, Wiper (V
W
6
BW
= +3 V or V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
Table I. Serial-Data Word Format
W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
pin where an adjacent V
DATA
B5
D5
MSB
2
W
5
) = No connect.
DD
JA
DD
= +5 V.
B4
D4
V
DD
W
DD
). CMOS logic level inputs result in minimum power dissipation.
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
= +5 V.
B3
D3
DD
W
, R
J
pin is making a full-scale voltage change.
MAX) . . . . . . . . +150 C
L
and C
B2
D2
DD
L
= +5 V.
. See Operation section.
J
DD
B1
D1
max–T
= +3 V or +5 V. Input logic should have a 1 V/ s minimum slew rate.
20 mA
A
B0
D0
LSB
2
)/
0
DD
JA
–3–
(DATA OUT)
V
(DATA IN)
CLK
OUT
SDI
CS
V
V
SDO
CLK
DD
0V
OUT
SDI
CS
0
0
0
1
1
1
V
V
OUT
R
DD
0V
RS
1
0
1
0
1
0
1
0
= t
A1
Figure 1b. Detail Timing Diagram
Figure 1c. Reset Timing Diagram
t
V
F
CSS
DD
0V
= 1 ns (10% to 90% of V
A0
1
0
Ax OR Dx
Figure 1a. Timing Diagram
A'x OR D'x
t
D5
PD MIN
D4
t
CH
D3
t
RS
DAC REGISTER LOAD
Ax OR Dx
t
1 LSB ERROR BAND
D2
DS
t
A'x OR D'x
CL
D1
WARNING!
t
DD
t
S
D0
DH
) and timed from a voltage level
1 LSB ERROR BAND
A
= V
DD
ESD SENSITIVE DEVICE
and V
t
t
t
PD MAX
CS1
DD
CSH
1 LSB
t
vs. logic voltage
S
B
t
CSW
= 0 V.
AD5203
W
= V
1 LSB
DD
/R