CAT5261YI-00-T2 ON Semiconductor, CAT5261YI-00-T2 Datasheet - Page 4

• Manufacturer Part Number: CAT5261YI-00-T2
• Description: IC POT DIG 100K 256T SPI 24TSSOP
• Manufacturer: ON Semiconductor

Specifications of CAT5261YI-00-T2

• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Resistance In Ohms: 100K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses and data to be written to the
CAT5261. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the CAT5261. During a read cycle, data is shifted
out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT5261. Opcodes, byte addresses or data present on the SI
pin are latched on the rising edge of the SCK. Data on the SO
pin is updated on the falling edge of the SCK.
A0, A1: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of four devices can be addressed on
a single bus. A match in the slave address must be made with
the address input in order to initiate communication with the
CAT5261.
R
The R
connections on a mechanical potentiometer.
R
The RW pins are equivalent to the wiper terminal of a
mechanical potentiometer.
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT5261 and
CS high disables the CAT5261. CS high takes the SO output
pin to high impedance and forces the devices into a Standby
mode (unless an internal write operation is underway). The
CAT5261 draws ZERO current in the Standby mode. A high
to low transition on CS is required prior to any sequence
being initiated. A low to high transition on CS after a valid
write sequence is what initiates an internal write cycle.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will allow
normal read/write operations when held high. When WP is
tied low, all non−volatile write operations to the Data
registers are inhibited (change of wiper control register is
allowed). WP going low while CS is still low will interrupt
a write to the registers. If the internal write cycle has already
been initiated, WP going low will have no effect on any write
operation.
H
W
, R
: Wiper
L
H
: Resistor End Points
and R
L
pins are equivalent to the terminal
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HOLD: Hold
The HOLD pin is used to pause transmission to the
CAT5261 while in the middle of a serial sequence without
having to retransmit entire sequence at a later time. To pause,
HOLD must be brought low while SCK is low. The SO pin
is in a high impedance state during the time the part is
paused, and transitions on the SI pins will be ignored. To
resume communication, HOLD is brought high, while SCK
is low. (HOLD should be held high any time this function is
not being used.) HOLD may be tied high directly to V
tied to V
WP: Write Protect Input
The WP pin when tied low prevents non−volatile writes to
the device (change of wiper control register is allowed) and
when tied high or left floating normal read/write operations
are allowed.
Serial Bus Protocol
protocol. The synchronous Serial Peripheral Interface (SPI)
helps the CAT5261 to interface directly with many of
today’s popular microcontrollers. The CAT5261 contains an
8−bit instruction register. The instruction set and the
operation codes are detailed in the Instruction Set Table 13
on page 9.
Device Operation
serial interface logic, two 8−bit wiper control registers and
eight 8−bit, non−volatile memory data registers. Each
resistor array contains 255 separate resistive elements
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (R
may be interchanged. The tap positions between and at the
ends of the series resistors are connected to the output wiper
terminals (R
going low the first byte will be received. The part is accessed
via the SI pin, with data being clocked in on the rising edge
of SCK. The first byte contains one of the six op−codes that
define the operation to be performed.
potentiometer is connected to its wiper terminal at a time and
is determined by the value of the wiper control register. Data
can be read or written to the wiper control registers or the
non−volatile memory data registers via the SPI bus.
Additional instructions allows data to be transferred
between the wiper control registers and each respective
potentiometer’s non−volatile data registers. Also, the device
can be instructed to operate in an “increment/decrement”
mode.
The CAT5261 supports the SPI bus data transmission
The CAT5261 is two resistor arrays integrated with an SPI
CMOS transistor switch. Only one tap point for each
CC
through a resistor.
W
) by a After the device is selected with CS
H
and R
L
). R
H
and R
L
are symmetrical and
CC
or