CAT5221WI-50-T1 ON Semiconductor, CAT5221WI-50-T1 Datasheet - Page 8

• Manufacturer Part Number: CAT5221WI-50-T1
• Description: IC POT DPP 50K 64TAP 20SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT5221WI-50-T1

• Taps: 64
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Write Operation
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte that defines the requested
operation of CAT5221. The instruction byte consist of a
four−bit opcode followed by two register selection bits and
two pot selection bits. After receiving another acknowledge
from the Slave, the Master device transmits the data to be
written into the selected register. The CAT5221
acknowledges once more and the Master generates the
STOP condition, at which time if a nonvolatile data register
is being selected, the device begins an internal programming
cycle to non−volatile memory. While this internal cycle is in
progress, the device will not respond to any request from the
Master device.
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
In the Write mode, the Master device sends the START
BUS ACTIVITY:
SDA LINE
MASTER
CAT5221
R
S
T
A
T
S
0
SLAVE/DPP
ADDRESS
Figure 6. Slave Address Bits
1
Figure 7. Write Timing
http://onsemi.com
0
C
A
K
INSTRUCTION
1
8
BYTE
A3
Acknowledge Polling
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write operation, the
CAT5221 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the slave address. If the CAT5221 is
still busy with the write operation, no ACK will be returned.
If the CAT5221 has completed the write operation, an ACK
will be returned and the host can then proceed with the next
instruction operation.
The disabling of the inputs can be used to take advantage
A2
C
A
K
DR WCR DATA
A1
A0
A
C
K
O
S
T
P
P