PIC18F66K22-I/PT Microchip Technology, PIC18F66K22-I/PT Datasheet - Page 183

• Manufacturer Part Number: PIC18F66K22-I/PT
• Description: 64kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F66K22-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.9
PORTH is an 8-bit wide, bidirectional I/O port. The
corresponding Data Direction and Output Latch registers
are TRISH and LATH.
All pins on PORTH are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
TABLE 12-15: PORTH FUNCTIONS
 2010 Microchip Technology Inc.
RH0/AN23
RH1/AN22
RH2/AN21
RH3/AN20
RH4/CCP9/
P3C/AN12/
C2INC
Legend:
Note:
Pin Name
PORTH, LATH and
TRISH Registers
PORTH is available only on the 80-pin
devices.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Function
C2INC
CCP9
AN23
AN22
AN21
AN20
AN12
RH0
RH1
RH2
RH3
RH4
P3C
Setting
TRIS
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
0
1
x
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
—
Preliminary
LATH<0> data output.
PORTH<0> data input.
A/D Input Channel 23.
Default input configuration on POR. Does not affect digital input.
LATH<1> data output.
PORTH<1> data input.
A/D Input Channel 22.
Default input configuration on POR. Does not affect digital input.
LATH<2> data output.
PORTH<2> data input.
A/D Input Channel 21.
Default input configuration on POR. Does not affect digital input.
LATH<3> data output.
PORTH<3> data input.
A/D Input Channel 20.
Default input configuration on POR. Does not affect digital input.
LATH<4> data output.
PORTH<4> data input.
CCP9 compare/PWM output. Takes priority over port data.
CCP9 capture input.
ECCP3 PWM Output C.
May be configured for tri-state during Enhanced PWM.
A/D Input Channel 12.
Default input configuration on POR. Does not affect digital input.
Comparator 2 Input C.
PIC18F87K22 FAMILY
EXAMPLE 12-8:
BANKSEL ANCON2
MOVLW
MOVWF
MOVLW
MOVWF
BANKSEL TRISH
MOVLW
MOVWF
CLRF
CLRF
0Fh
ANCON2
0Fh
ANCON1
0CFh
TRISH
PORTH
LATH
Description
; Select bank with ANCON2 register
; Configure PORTH as
; digital I/O
; Configure PORTH as
; digital I/O
; Select bank with TRISH register
; Value used to
; initialize data
; direction
; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
; Initialize PORTH by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
INITIALIZING PORTH
DS39960B-page 183