CY62128EV30LL-55SXET Cypress Semiconductor Corp, CY62128EV30LL-55SXET Datasheet - Page 7

• Manufacturer Part Number: CY62128EV30LL-55SXET
• Description: CY62128EV30LL-55SXET
• Manufacturer: Cypress Semiconductor Corp
• Series: -r

Specifications of CY62128EV30LL-55SXET

• Format - Memory: RAM
• Memory Type: SRAM
• Memory Size: 1M (128K x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-SOIC (0.445", 11.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Switching Waveforms
Notes
Document #: 001-65528 Rev. **
19. The internal write time of the memory is defined by the overlap of WE, CE = V
20. The device is continuously selected. OE, CE
21. WE is HIGH for read cycle.
22. CE is the logical combination of CE
23. Address valid before or similar to CE
24. Data I/O is high impedance if OE = V
25. If CE
26. During this period, the I/Os are in output state. Do not apply input signals.
DATA OUT
Current
Address
Data Out
ADDRESS
Address
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Supply
DATA I/O
1
V
CE
OE
goes HIGH or CE
CC
WE
OE
CE
NOTE 26
2
Previous Data Valid
goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
High Impedance
t
PU
1
t
1
and CE
IH
Figure 6. Read Cycle 1 Address transition controlled
LZCE
t
SA
transition LOW and CE
.
t
HZOE
Figure 8. Write Cycle No. 1 WE controlled
Figure 7. Read Cycle No. 2 OE controlled
t
t
ACE
LZOE
1
2
. When CE
= V
t
OHA
50%
IL
t
DOE
, CE
2
1
= V
is LOW and CE
t
IH
AA
2
t
.
AW
transition HIGH.
t
t
SCE
RC
2
t
WC
is HIGH, CE is LOW; when CE
IL
. All signals must be ACTIVE to initiate a write and any of these signals can
t
RC
RC
t
t
PWE
DATA VALID
SD
CY62128EV30 MoBL
DATA VALID
[19, 22, 24, 25]
[21, 22, 23]
1
is HIGH or CE
[20, 21]
Data Valid
t
t
HZOE
HA
t
HD
2
t
is LOW, CE is HIGH.
HZCE
t
PD
50%
®
Automotive
Impedance
High
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