LMZ23605TZ National Semiconductor, LMZ23605TZ Datasheet - Page 17

• Manufacturer Part Number: LMZ23605TZ
• Description: POWER MODULE, 36V, 5A, 7TO-PMOD
• Manufacturer: National Semiconductor

Specifications of LMZ23605TZ

• Primary Input Voltage: 36V
• No. Of Outputs: 1
• Output Voltage: 6V
• Output Current: 5A
• Voltage Regulator Case Style: TO-PMOD
• No. Of Pins: 7
• Operating Temperature Range: -40°C To +125°C
• Rohs Compliant: Yes

PC BOARD LAYOUT GUIDELINES
PC board layout is an important part of DC-DC converter de-
sign. Poor board layout can disrupt the performance of a DC-
DC converter and surrounding circuitry by contributing to EMI,
ground bounce and resistive voltage drop in the traces. These
can send erroneous signals to the DC-DC converter resulting
in poor regulation or instability. Good layout can be imple-
mented by following a few simple design rules. A good ex-
ample layout is shown in Figure 5.
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize
the high di/dt paths during PC board layout as shown in the
figure above. The high current loops that do not overlap have
high di/dt content that will cause observable high frequency
noise on the output pin if the input capacitor (Cin1) is placed
at a distance away from the LMZ23605. Therefore place
C
exposed pad. This will minimize the high di/dt area and reduce
radiated EMI. Additionally, grounding for both the input and
output capacitor should consist of a localized top side plane
that connects to the PGND exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and en-
able components should be routed to the AGND pin of the
device. This prevents any switched or load currents from
flowing in the analog ground traces. If not properly handled,
poor grounding can result in degraded load regulation or er-
ratic output voltage ripple behavior. Additionally provide the
single point ground connection from pin 4 (AGND) to EP/
PGND.
3. Minimize trace length to the FB pin.
Both feedback resistors, R
close to the FB pin. Since the FB node is high impedance,
maintain the copper area as small as possible. The traces
from R
LMZ23605 to minimize possible noise pickup.
4. Make input and output bus connections as wide as
possible.
This reduces any voltage drops on the input or output of the
converter and maximizes efficiency. To optimize voltage ac-
curacy at the load, ensure that a separate feedback voltage
sense trace is made to the load. Doing so will correct for volt-
age drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad
to the ground plane on the bottom PCB layer. If the PCB has
a plurality of copper layers, these thermal vias can also be
employed to make connection to inner layer heat-spreading
IN1
as close as possible to the LMZ23605 VIN and PGND
FBT
, R
FBB
should be routed away from the body of the
FIGURE 3.
FBT
and R
FBB
should be located
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ground planes. For best results use a 6 x 10 via array with
minimum via diameter of 10mils (254 μm) thermal vias spaced
39mils (1.0 mm). Ensure enough copper area is used for heat-
sinking to keep the junction temperature below 125°C.
Additional Features
SYNCHRONIZATION INPUT
The PWM switching frequency can be synchronized to an ex-
ternal frequency source. If this feature is not used, connect
this input either directly to ground, or connect to ground
through a resistor of 1.5 kΩ ohm or less. The allowed syn-
chronization frequency range is 650kHz to 950 kHz. The
typical input threshold is 1.4V transition level. Ideally the input
clock should overdrive the threshold by a factor of 2, so direct
drive from 3.3V logic via a 1.5kΩ Thevenin source resistance
is recommended. Note that applying a sustained “logic 1” cor-
responds to zero hertz PWM frequency and will cause the
module to stop switching.
OUTPUT OVER-VOLTAGE PROTECTION
If the voltage at FB is greater than a 0.86V internal reference,
the output of the error amplifier is pulled toward ground, caus-
ing V
CURRENT LIMIT
The LMZ23605 is protected by both low side (LS) and high
side (HS) current limit circuitry. The LS current limit detection
is carried out during the off-time by monitoring the current
through the LS synchronous MOSFET. Referring to the Func-
tional Block Diagram, when the top MOSFET is turned off, the
inductor current flows through the load, the PGND pin and the
internal synchronous MOSFET. If this current exceeds 5.4A
(typical) the current limit comparator disables the start of the
next switching period. Switching cycles are prohibited until
current drops below the limit. It should also be noted that d.c.
current limit is dependent on both duty cycle as illustrated in
the graph in the typical performance section. The HS current
limit monitors the current of top side MOSFET. Once HS cur-
rent limit is detected (7A typical) , the HS MOSFET is shut off
immediately, until the next cycle. Exceeding HS current limit
causes V
limit is that f
THERMAL PROTECTION
The junction temperature of the LMZ23605 should not be al-
lowed to exceed its maximum ratings. Thermal protection is
implemented by an internal Thermal Shutdown circuit which
activates at 165 °C (typ) causing the device to enter a low
power standby state. In this state the main MOSFET remains
off causing V
discharged to ground. Thermal protection helps prevent
catastrophic failures for accidental device overheating. When
the junction temperature falls back below 150 °C (typ Hyst =
15°C) the SS pin is released, V
operation resumes.
Applications requiring maximum output current especially
those at high input voltage may require additional derating at
elevated temperatures.
PRE-BIASED STARTUP
The LMZ23605 will properly start up into a pre-biased output.
This startup situation is common in multiple rail logic applica-
tions where current paths may exist between different power
rails during the startup sequence. The following scope cap-
ture shows proper behavior in this mode. Trace one is Enable
O
to fall.
O
to fall. Typical behavior of exceeding LS current
SW
O
drops to 1/2 of the operating frequency.
to fall, and additionally the C
O
rises smoothly, and normal
SS
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capacitor is