DS1805E-010+T&R Maxim Integrated Products, DS1805E-010+T&R Datasheet - Page 4

• Manufacturer Part Number: DS1805E-010+T&R
• Description: IC POT DIG ADDRESS 10K 14-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of DS1805E-010+T&R

• Taps: 256
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 750 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC ELECTRICAL CHARACTERISTICS
(V
Addressable Digital Potentiometer
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: A fast mode device can be used in a standard mode system, but the requirement t
Note 11: After this period, the first clock pulse is generated.
Note 12: The maximum t
Note 13: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
Note 14: C
4
CC
_____________________________________________________________________
= 2.7V to 5.5V, T
All voltages are referenced to ground.
I
Address inputs A0, A1, and A2 should be connected to either V
I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
I
Valid at +25°C only.
Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper position.
Relative linearity is used to determine the change in voltage between successive tap positions.
-3dB cutoff frequency characteristics for the DS1805 depend on potentiometer total resistance: DS1805-010, 1MHz;
DS1805-50, 200kHz; DS1805-100, 100kHz.
will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line t
1250ns before the SCL line is released.
in order to bridge the undefined region of the falling edge of SCL.
CC
STBY
B
—total capacitance of one bus line in picofarads, timing referenced to (0.9)(V
specified with SDA pin open. SCL = 400kHz clock rate.
specified with SDA = SCL = V
A
= -40°C to +85°C)
HD:DAT
has only to be met if the device does not stretch the low period (t
CC
= 5.0V.
CC
or GND, depending on the desired address selections.
CC
is switched off.
CC
RMAX
SU:DAT
) and (0.1)(V
+ t
LOW
> 250ns must then be met. This
SU:DAT
) of the SCL signal.
CC
IHMIN
= 1000ns + 250ns =
).
of the SCL signal)