X9250US24Z Intersil, X9250US24Z Datasheet - Page 9
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X9250US24Z
Manufacturer Part Number
X9250US24Z
Description
IC XDCP QUAD 256TP 50K 24-SOIC
Manufacturer
Intersil
Series
XDCP™r
Datasheet
1.X9250US24.pdf
(20 pages)
Specifications of X9250US24Z
Taps
256
Resistance (ohms)
50K
Number Of Circuits
4
Temperature Coefficient
300 ppm/°C Typical
Memory Type
Non-Volatile
Interface
SPI, 3-Wire Serial
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Resistance In Ohms
50K
Track Taper
Linear
Resistance Tolerance
± 20%
No. Of Steps
256
Supply Voltage Range
4.5V To 5.5V
Control Interface
SPI
No. Of Pots
Quad
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
X9250US24Z
Manufacturer:
Intersil
Quantity:
150
Company:
Part Number:
X9250US24Z
Manufacturer:
Intersil
Quantity:
500
Company:
Part Number:
X9250US24Z-2.7T1
Manufacturer:
PANASONIC
Quantity:
4 430
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
Read Wiper Counter Register(WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Falling
Falling
Falling
Falling
Falling
Edge
Edge
Edge
Edge
Edge
CS
CS
CS
CS
CS
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
device type
device type
0 1 0 1 0 0
device type
0 1 0 1 0 0
device type
0 1 0 1 0 0
device type
0 1 0 1 0 0
0 1 0 1 0 0
identifier
identifier
identifier
identifier
identifier
addresses
addresses
addresses
addresses
addresses
device
device
device
device
device
9
A
1
A
1
A
A
1
1
A
1
A
A
0
0
A
0
A
0
A
0
1 1 0 1 R1 R0 P1 P0
1 1 0 0
1 0 0 1 0 0
1 0 1 0 0 0
instruction
instruction
1 0 1 1
instruction
instruction
instruction
opcode
opcode
opcode
opcode
opcode
DR and WCR
R
1
DR and WCR
DR and WCR
R
1
addresses
addresses
addresses
addresses
addresses
R
0
WCR
WCR
R
0
X9250
P
1
P
1
P
1
P
1
P
P
0
0
P
0
P
0
W
W
P
P
7
7
W
P
7
W
(sent by X9250 on SO)
P
7
Rising
(sent by X9250 on SO)
(sent by host on SI)
Edge
(sent by Host on SI)
W
W
P
6
P
6
CS
W
P
6
W
P
6
wiper position
W
P
W
5
P
5
W
P
Data Byte
5
W
P
5
Data Byte
Data Byte
W
P
4
W
P
4
W
P
4
W
P
4
W
P
3
W
P
3
W
P
3
W
P
3
W
P
2
W
P
2
W
P
2
W
P
2
W
P
1
W
P
1
W
P
1
W
P
1
W
P
0
W
P
0
W
P
0
W
P
0
Rising
Edge
Rising
Rising
Edge
CS
Edge
Rising
Edge
CS
CS
CS
HIGH-VOLTAGE
WRITE CYCLE
August 29, 2006
FN8165.3