X9429WV14IZT1 Intersil, X9429WV14IZT1 Datasheet - Page 7

• Manufacturer Part Number: X9429WV14IZT1
• Description: IC XDCP SGL 64-TAP 10K 14-TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9429WV14IZT1

• Taps: 64
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read Wiper Counter Register (read the current wiper
position of the selected pot), write Wiper Counter Register
(change current wiper position of the selected pot), read
Data Register (read the contents of the selected nonvolatile
register) and write Data Register (write a new value to the
selected Data Register). The sequence of operations is
shown in Figure 4.
The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9429 has responded with an acknowledge, the master can
Read Wiper Counter Register
Write Wiper Counter Register
Read Data Register
Write Data Register
XFR Data Register to Wiper
Counter Register
XFR Wiper Counter
Register to Data Register
Increment/Decrement Wiper
Counter Register
SCL
SDA
SCL
SDA
INSTRUCTION
S
T
A
R
T
S
T
A
R
T
0
0
1
1
0
0
1
1
A3 A2 0
7
I
1
1
1
1
1
1
0
A3
3
A2
I
0
0
0
1
1
1
0
2
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
0
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
A0
I
0
1
1
0
0
1
1
1
INSTRUCTION SET
A0
A
C
K
I
1
1
0
0
1
0
0
0
I3
A
C
K
TABLE 1. INSTRUCTION SET
1/0
1/0
1/0
1/0
R
0
0
0
I3
I2
1
I2
1/0
1/0
1/0
1/0
R
I1
0
0
0
0
X9429
I0
I1
X
0
0
0
0
0
0
0
1
R1 R0
I0
X
clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (t
selected wiper will move one resistor segment towards the
V
SDA is LOW, the selected wiper will move one resistor
segment towards the V
the sequence and timing for this operation are shown in
Figures 5 and 6 respectively.
NOTE: (1)1/0 = data is one or zero
0
0
0
0
0
0
0
R1
0
H
/R
0
Read the contents of the Wiper Counter Register
Write new value to the Wiper Counter Register
Read the contents of the Data Register pointed to by R
Write new value to the Data Register pointed to by R
Transfer the contents of the Data Register pointed to by R
to its Wiper Counter Register
Transfer the contents of the Wiper Counter Register to the Data
Register pointed to by R
Enable Increment/decrement of the Wiper Counter Register
R0
H
terminal. Similarly, for each SCL clock pulse while
0
0
A
C
K
0
0
A
C
K
0
N
C
1
I
L
/R
D5 D4
L
OPERATION
1
N
C
2
I
- R
terminal. A detailed illustration of
HIGH
0
D3 D2
) while SDA is HIGH, the
N
C
n
I
D
E
C
1
D1 D0
D
E
C
October 13, 2008
n
A
C
K
1
S
T
O
P
S
T
O
P
- R
1
FN8248.3
1
- R
0
- R
0
0