AD8403ARUZ1 Analog Devices Inc, AD8403ARUZ1 Datasheet - Page 10
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AD8403ARUZ1
Manufacturer Part Number
AD8403ARUZ1
Description
IC POT DGTL QUAD 1K 24-TSSOP
Manufacturer
Analog Devices Inc
Specifications of AD8403ARUZ1
Temperature Coefficient
500 ppm/°C Typical
Taps
256
Resistance (ohms)
1K
Number Of Circuits
4
Memory Type
Volatile
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Resistance In Ohms
1.00K
End To End Resistance
1kohm
No. Of Steps
256
Supply Voltage Range
2.7V To 5.5V
Control Interface
Serial, 3-Wire
No. Of Pots
Quad
Potentiometer Ic Case
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD8403EVAL - BOARD EVAL FOR AD8403
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD8403ARUZ1
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD8403ARUZ10
Manufacturer:
ADI
Quantity:
1 140
Part Number:
AD8403ARUZ10
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD8403ARUZ10-REEL
Manufacturer:
AD
Quantity:
1 500
Part Number:
AD8403ARUZ10-REEL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD8403ARUZ100
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD8403ARUZ100-REEL
Manufacturer:
AD
Quantity:
1 900
Part Number:
AD8403ARUZ100-REEL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD8400/AD8402/AD8403
ELECTRICAL CHARACTERISTICS—ALL VERSIONS
V
Table 4.
Parameter
SWITCHING CHARACTERISTICS
1
2
3
4
TIMING DIAGRAMS
(DATA OUT)
V
CLK
Typicals represent average readings at 25°C and V
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
See the timing diagram in
timed from a voltage level of 1.6 V. Switching characteristics are measured using V
of 1 V/µs should be maintained.
Propagation delay depends on the value of V
OUT
SDI
DD
CS
(DATA IN)
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
CS Setup Time
CS High Pulse Width
Reset Pulse Width
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
V
= 3 V ± 10% or 5 V ± 10%, V
V
DD
0V
SDO
CLK
1
0
1
0
1
0
OUT
SDI
CS
V
0V
DD
1
0
1
0
1
0
1
0
A1
A0
Ax OR Dx
A'x OR D'x
t
D7
PD_MIN
t
Figure 4. Detailed Timing Diagram
CSS
D6
Figure 3. Timing Diagram
t
CH
Figure 3
D5
A'x OR D'x
Ax OR Dx
t
DS
D4
t
for location of measured values. All input control voltages are specified with t
CL
2, 3
D3
DAC REGISTER LOAD
4
A
t
DH
D2
= V
DD
D1
DD
±1% ERROR BAND
t
, R
CSH
, V
L
DD
, and C
D0
B
= 5 V.
t
= 0 V, −40°C ≤ T
PD_MAX
t
CS1
L
Symbol
t
t
t
t
t
t
t
t
t
(see the
t
CH
DS
DH
PD
CSS
CSW
RS
CSH
CS1
S
t
CSW
, t
CL
Applications
±1%
Rev. D | Page 10 of 32
A
Conditions
Clock level high or low
R
≤ +125°C, unless otherwise noted.
L
= 1 kΩ to 5 V, C
section).
DD
= 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate
L
≤ 20 pF
V
OUT
RS
V
DD
V
DD
/2
1
0
Figure 5. Reset Timing Diagram
R
= t
F
= 1 ns (10% to 90% of V
±1% ERROR BAND
Min
10
5
5
1
10
10
50
0
10
t
RS
t
S
Typ
1
DD
) and
±1%
Max
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns