AD5252BRUZ50 Analog Devices Inc, AD5252BRUZ50 Datasheet - Page 15

• Manufacturer Part Number: AD5252BRUZ50
• Description: IC POT DGTL DL 50K 256P 14TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5252BRUZ50

• Memory Type: Non-Volatile
• Temperature Coefficient: 650 ppm/°C Typical
• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V, ±2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 50K
• End To End Resistance: 50kohm
• Track Taper: Linear
• Resistance Tolerance: ± 20%
• No. Of Steps: 256
• Control Interface: Serial, I2C, 2-Wire
• No. Of Pots: Dual
• Supply Voltage Range: ± 2.25V To ± 2.75V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD5252EVAL - BOARD EVAL FOR AD5252
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

I
Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/ W = 0, CMD/ REG = 0, EE/ RDAC = 0)
A4
0
0
0
0
0
:
:
0
2
C INTERFACE DETAIL DESCRIPTION
A3
0
0
0
0
0
:
:
1
S
0
RDAC SLAVE ADDRESS
1
0
A2
0
0
0
0
1
:
:
1
1
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW
CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW
EE/RDAC = EEMEM REGISTER, LOGIC HIGH/RDAC REGISTER, LOGIC LOW
A4, A3, A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES
S
1
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
0
A
D
1
1
SLAVE ADDRESS
A
D
0
0 WRITE
0
A1
0
0
1
1
0
:
:
1
0
1
A
1
0 REG
CMD/
REG
A
D
1
A
D
0
0 WRITE
A0
0
1
0
1
0
:
:
1
RDAC INSTRUCTIONS
0
0
AND ADDRESS
Figure 28. Consecutive Write Mode
RDAC
EE/
A
Figure 27. Single Write Mode
0 REG
CMD/
REG
Rev. B | Page 15 of 28
A
4
RDAC
Reserved
RDAC1
Reserved
RDAC3
Reserved
:
:
Reserved
A
3
0
A
2
INSTRUCTIONS
AND ADDRESS
RDAC
EE/
A
1
A
0
A
4
A
A
3
A
2
RDAC1
DATA
A
1
Data Byte Description
6-/8-bit wiper setting (2 MSB of AD5251 are X)
6-/8-bit wiper setting (2 MSB of AD5251 are X)
A
0
A
A
ACKNOWLEDGE)
ACKNOWLEDGE)
DATA
(N BYTES +
X
(1 BYTE +
DATA
A
A/
A
RDAC3
DATA
P
AD5251/AD5252
A/
A
P