MCP41100-E/P Microchip Technology, MCP41100-E/P Datasheet - Page 22
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MCP41100-E/P
Manufacturer Part Number
MCP41100-E/P
Description
IC POT DGTL 100K 1CH SPI 8DIP
Manufacturer
Microchip Technology
Datasheet
1.MCP41010-ISN.pdf
(32 pages)
Specifications of MCP41100-E/P
Package / Case
8-DIP (0.300", 7.62mm)
Taps
256
Resistance (ohms)
100K
Number Of Circuits
1
Temperature Coefficient
800 ppm/°C Typical
Memory Type
Non-Volatile
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Through Hole
Resistance In Ohms
100K
Number Of Pots
Single
Taps Per Pot
256
Resistance
100 KOhms
Buffered Wiper
Buffered
Digital Interface
Serial (SPI)
Operating Supply Voltage
3.3 V or 5 V
Supply Current
0.34 mA (Typ)
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Description/function
256 Step SPI 100k Ohm with SPI Interface
Mounting Style
Through Hole
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCP41100-E/P
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
MCP41100-E/P
Manufacturer:
MICROCHIP
Quantity:
12 000
MCP41XXX/42XXX
5.8
It is possible to operate the devices in SPI modes 0,0
and 1,1. The only difference between these two modes
is that, when using mode 1,1, the clock idles in the high
state, while in mode 0,0, the clock idles in the low state.
In both modes, data is clocked into the devices on the
rising edge of SCK and data is clocked out the SO pin
once the falling edge of SCK. Operations using mode
0,0 are shown in Figure 5-1. The example in
Figure 5-5 shows mode 1,1.
FIGURE 5-5:
DS11195C-page 22
SCK
CS†
SO‡
SI
Using the MCP41XXX/42XXX in
SPI Mode 1,1
†
‡
There must always be multiples of 16 clocks while CS is low or commands will abort.
The serial data out pin (SO) is only available on the MCP42XXX device.
X
1
Don’t
Care
Bits
Timing Diagram for SPI Mode 1,1 Operation.
2
X
COMMAND BYTE
Command
C1
3
Data is always latched in
on the rising edge of SCK.
Bits
C0
4
First 16 bits Shifted out will always be zeros
5
X
Don’t
Care
Bits
X
6
P1* P0
Channel
7
Select
Bits
8
D7
9
10
D6
11
D5
Data is always clocked out the SO
pin after the falling edge of SCK.
New Register Data
DATA BYTE
12
D4
13
D3
14
D2
15
D1
16
D0
X
2003 Microchip Technology Inc.
Data Registers are
loaded on rising
edge of CS. Shift
register is loaded
with zeros at this time.
SO pin will always
drive low when CS
goes high.