MCP4161T-104E/SN Microchip Technology, MCP4161T-104E/SN Datasheet - Page 55
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
MCP4161T-104E/SN
Manufacturer Part Number
MCP4161T-104E/SN
Description
IC POT DGTL SNGL 100K SPI 8SOIC
Manufacturer
Microchip Technology
Specifications of MCP4161T-104E/SN
Package / Case
8-SOIC (3.9mm Width)
Taps
257
Resistance (ohms)
100K
Number Of Circuits
1
Temperature Coefficient
150 ppm/°C Typical
Memory Type
Non-Volatile
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Resistance In Ohms
100K
Number Of Pots
Single
Taps Per Pot
256
Resistance
100 KOhms
Wiper Memory
Non Volatile
Digital Interface
Serial (4-Wire, SPI)
Operating Supply Voltage
2.5 V, 3.3 V, 5 V
Supply Current
550 uA
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
7.8
The Decrement Command is an 8-bit command. The
Decrement Command can only be issued to volatile
memory locations. The format of the command is
shown in
An Decrement Command to the volatile memory
location changes that location after a properly
formatted command (8-clocks) have been received.
Decrement commands provide a quick and easy
method to modify the value of the volatile wiper location
by -1 with minimal overhead.
FIGURE 7-8:
SDI and SDO States.
© 2007 Microchip Technology Inc.
SDI
SDO
Note:
Note 1: Only functions when writing the volatile
D
Decrement Wiper
A
Normal and High Voltage
3
1
1
2: Valid Address/Command combination.
3: Invalid Address/Command combination
4: If a Command Error (CMDERR) occurs
Figure
(DECR COMMAND (n+1))
Table 7-2
the Decrement Wiper command. Other
addresses are invalid.
A
D
wiper registers (AD3:AD0) 0h and 1h.
all following SDO bits will be low until the
CMDERR condition is cleared.
(the CS pin is forced to the inactive
state).
at this bit location (*), then all following
SDO bits will be driven low until the CS
pin is driven inactive (V
2
1
1
COMMAND BYTE
7-6.
A
D
1
1
1
A
D
0
1
1
shows the valid addresses for
Decrement Command -
1
1
1
0
1 1* 1 Note 1, 2
1
X
0
IH
X
0 Note 1, 3
).
MCP414X/416X/424X/426X
7.8.1
Typically the CS pin starts at the inactive state (V
may be already be in the active state due to the com-
pletion of another command.
Figure 6-7
waveforms for a single Decrement. The decrement
operation requires that the CS pin be in the active state
(V
state (V
Then the 8-bit Decrement Command (Command Byte)
is clocked in on the SDI pin by the SCK pins. The SDO
pin drives the CMDERR bit on the 7th clock.
The wiper value will decrement from the wipers Full
Scale value (100h on 8-bit devices and 80h on 7-bit
devices).
(8-bit =101h to 1FFh, 7-bit = 81h to FFh), the
decrement command is disabled. If the Wiper register
has a Zero Scale value (000h), then the wiper value will
not decrement. See
on the Decrement Command vs. the current volatile
wiper value.
The Decrement commands only require the Decrement
command byte, while the CS pin is active (V
for a single decrement.
After the wiper is decremented to the desired position,
the CS pin should be forced to V
unexpected transitions on the SCK pin do not cause
the wiper setting to change. Driving the CS pin to V
should occur as soon as possible (within device
specifications) after the last desired decrement occurs.
TABLE 7-5:
Current Wiper
3FFh
081h
080h
07Fh
041h
040h
03Fh
001h
000h
IL
7-bit
Pot
or V
Setting
IH
IHH
) and is driven to the active state (V
). Typically the CS pin will be in the inactive
3FFh
101h
100h
0FFh
080h
07Fh
000h
8-bit
Above
SINGLE DECREMENT
081
001
Pot
through
DECREMENT OPERATION VS.
VOLATILE WIPER VALUE
Reserved
(Full Scale (W = A))
Full Scale (W = A)
W = N
W = N (Mid-Scale)
W = N
Zero Scale (W = B) No
Table 7-4
the
Properties
Wiper (W)
Figure 6-8
wipers
for additional information
Full
IH
DS22059A-page 55
show
to ensure that
No
Yes
Yes
Scale
Decrement
Operates?
Command
IL
IL
or V
possible
or V
IH
value
), but
IHH
IHH
IH
).
)