MCP4132-502E/MS Microchip Technology, MCP4132-502E/MS Datasheet - Page 49

• Manufacturer Part Number: MCP4132-502E/MS
• Description: IC RHEO DGTL SNGL 5K SPI 8MSOP
• Manufacturer: Microchip Technology

Specifications of MCP4132-502E/MS

• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Taps: 129
• Resistance (ohms): 5K
• Number Of Circuits: 1
• Temperature Coefficient: 150 ppm/°C Typical
• Memory Type: Volatile
• Interface: SPI Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Resistance In Ohms: 5K
• Number Of Pots: Single
• Taps Per Pot: 128
• Resistance: 5 KOhms
• Wiper Memory: Volatile
• Digital Interface: Serial (SPI)
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Supply Current: 1 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

7.2
Only the Read Command and the Write Command use
the Data Byte, see
concatenate the 8-bits of the Data Byte with the one
data bit (D8) contained in the Command Byte to form
9-bits of data (D8:D0). The Command Byte format
supports up to 9-bits of data so that the 8-bit resistor
network can be set to Full-Scale (100h or greater). This
allows wiper connections to Terminal A and to
Terminal B.
The D9 bit is currently unused, and corresponds to the
position on the SDO data of the CMDERR bit.
7.3
The CMDERR bit indicates if the four address bits
received (AD3:AD0) and the two command bits
received (C1:C0) are a valid combination (see
Table
is valid and low if the combination is invalid.
SPI commands that do not have a multiple of 8 clocks
are ignored.
Once an error condition has occurred, any following
commands are ignored. All following SDO bits will be
low until the CMDERR condition is cleared by forcing
the CS pin to the inactive state (V
© 2008 Microchip Technology Inc.
4-1). The CMDERR bit is high if the combination
Data Byte
Error Condition
Figure
7-1. These commands
IH
).
MCP413X/415X/423X/425X
7.3.1
All SPI transmissions must have the correct number of
SCK pulses to be executed. The command is not
executed until the complete number of clocks have
been received. If the CS pin is forced to the inactive
state (V
mands are not executed.
SPI is more susceptible to noise than other bus
protocols. The most likely case is that this noise
corrupts the value of the data being clocked into the
MCP4XXX or the SCK pin is injected with extra clock
pulses. This may cause data to be corrupted in the
device, or a command error to occur, since the address
and command bits were not a valid combination. The
extra SCK pulse will also cause the SPI data (SDI) and
clock (SCK) to be out of sync. Forcing the CS pin to the
inactive state (V
interface will ignore activity on the SDI and SCK pins
until the CS pin transition to the active state is detected
(V
IH
Note 1: When data is not being received by the
to V
IH
IL
2: It is also recommended that long
) the serial interface is reset. Partial com-
or V
ABORTING A TRANSMISSION
MCP4XXX, It is recommended that the
CS pin be forced to the inactive level (V
continuous command strings should be
broken down into single commands or
shorter continuous command strings.
This reduces the probability of noise on
the SCK pin corrupting the desired SPI
commands.
IH
IH
to V
) resets the serial interface. The SPI
IHH
).
DS22060B-page 49
IL
)