MCP4141-503E/SN Microchip Technology, MCP4141-503E/SN Datasheet - Page 30
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MCP4141-503E/SN
Manufacturer Part Number
MCP4141-503E/SN
Description
IC POT DGTL SNGL 50K SPI 8SOIC
Manufacturer
Microchip Technology
Datasheet
1.MCP4161-502ESN.pdf
(88 pages)
Specifications of MCP4141-503E/SN
Memory Type
Non-Volatile
Taps
129
Resistance (ohms)
50K
Number Of Circuits
1
Temperature Coefficient
150 ppm/°C Typical
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Resistance In Ohms
50K
End To End Resistance
50kohm
Resistance Tolerance
± 20%
No. Of Steps
129
Supply Voltage Range
2.7V To 5.5V
Control Interface
SPI
No. Of Pots
Single
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MCP414X/416X/424X/426X
4.2.1
This memory can be grouped into two uses of
non-volatile memory. These are:
•
•
The non-volatile wipers starts functioning below the
devices V
4.2.1.1
These locations allow the user to store up to 10 (9-bit)
locations worth of information.
4.2.1.2
These locations contain the wiper values that are
loaded into the corresponding volatile wiper register
whenever the device has a POR/BOR event. There are
up to two registers, one for each resistor network.
The non-volatile wiper register enables stand-alone
operation of the device (without Microcontroller control)
after being programmed to the desired value.
4.2.1.3
The Non-Volatile Wiper values will be initialized to
mid-scale value. This is shown in
The General purpose EEPROM memory will be
programmed to a default value of 0xFF.
It is good practice in the manufacturing flow to
configure the device to your desired settings.
TABLE 4-2:
DS22059B-page 30
-502
-103
-503
-104
General Purpose Registers
Non-Volatile Wiper Registers
100.0 kΩ Mid-scale
10.0 kΩ
50.0 kΩ
5.0 kΩ
POR
NON-VOLATILE MEMORY
(EEPROM)
General Purpose Registers
Non-Volatile Wiper Registers
Factory Initialization of Non-Volatile
Memory (EEPROM)
/V
BOR
DEFAULT FACTORY
SETTINGS SELECTION
Mid-scale
Mid-scale
Mid-scale
trip point.
8-bit 7-bit
80h
80h
80h
80h
Wiper
Code
Table
40h
40h
40h
40h
4-2.
Disabled
Disabled
Disabled
Disabled
4.2.1.4
There are 3 non-volatile bits that are not directly
mapped into the address space. These bits control the
following functions:
• EEPROM Write Protect
• WiperLock Technology for Non-Volatile Wiper 0
• WiperLock Technology for Non-Volatile Wiper 1
The operation of WiperLock Technology is discussed in
Section 5.3. The state of the WL0, WL1, and WP bits
is reflected in the STATUS register (see
EEPROM Write Protect
All internal EEPROM memory can be Write Protected.
When EEPROM memory is Write Protected, Write
commands to the internal EEPROM are prevented.
Write Protect (WP) can be enabled/disabled by two
methods. These are:
• External WP Hardware pin (MCP42X1 devices
• Non-Volatile configuration bit
High Voltage commands are required to enable and
disable the nonvolatile WP bit. These commands are
shown in Section 7.9 “Modify Write Protect or Wip-
erLock Technology (High Voltage)”.
To write to EEPROM, both the external WP pin and the
internal WP EEPROM bit must be disabled. Write
Protect does not block commands to the volatile
registers.
4.2.2
There are four Volatile Memory locations. These are:
• Volatile Wiper 0
• Volatile Wiper 1
• Status Register
• Terminal Control (TCON) Register
The volatile memory starts functioning at the RAM
retention voltage (V
only)
(Dual Resistor Network devices only)
VOLATILE MEMORY (RAM)
Special Features
RAM
).
© 2008 Microchip Technology Inc.
Register
4-1).