X9420WV14I-2.7 Intersil, X9420WV14I-2.7 Datasheet - Page 9

• Manufacturer Part Number: X9420WV14I-2.7
• Description: IC DIGITAL POT 10K 64TP 14TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9420WV14I-2.7

• Taps: 64
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Read the contents of the Register pointed to by R1 - R0.
Write Data Register (DR)
Write a new value to the Register pointed to by R1 - R0.
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer the contents of the Register pointed to by R1 - R0 to the WCR.
Falling
Falling
Falling
Falling
Falling
Edge
Edge
Edge
Edge
Edge
CS
CS
CS
CS
CS
(2) WPx refers to wiper position data in the Wiper Counter Register
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
device type
device type
0 1 0 1 1 1 0
device type
0 1 0 1 1 1 0
device type
0 1 0 1 1 1 0
device type
0 1 0 1 1 1 0
0 1 0 1 1 1 0
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
identifier
identifier
identifier
identifier
identifier
addresses
addresses
addresses
addresses
addresses
device
device
device
device
device
9
A
0
A
0
A
A
A
0
0
0
1 1 0 0
1 1 0 1
instruction
instruction
1 0 1 1
1 0 0 1 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0 0
instruction
instruction
instruction
opcode
opcode
opcode
opcode
opcode
R
1
R
1
addresses
addresses
R
1
addresses
register
register
R
register
0
R
0
R
0
0 0 0 0
0 0
0 0 0 0
X9420
Rising
Edge
CS
(sent by host on SI)
(sent by X9420 on SO)
(sent by X9420 on SO)
(sent by Host on SI)
W
P
5
Data Byte
wiper position
W
W
W
P
P
P
5
5
5
Data Byte
Data Byte
W
P
4
W
W
W
P
P
P
4
4
4
W
P
3
W
W
W
P
P
P
3
3
3
W
P
2
W
W
W
P
P
P
2
2
2
W
P
1
W
W
W
P
P
P
1
1
1
W
P
0
W
W
W
P
P
P
0
0
0
Rising
Edge
CS
Rising
Rising
Rising
Edge
Edge
Edge
CS
CS
CS
HIGH-VOLTAGE
WRITE CYCLE
April 26, 2006
FN8195.1