ISL90840WIV2027Z Intersil, ISL90840WIV2027Z Datasheet

IC POT DGTL QUAD 10K OHM 20TSSOP

ISL90840WIV2027Z

Manufacturer Part Number
ISL90840WIV2027Z
Description
IC POT DGTL QUAD 10K OHM 20TSSOP
Manufacturer
Intersil
Series
XDCP™r
Datasheet

Specifications of ISL90840WIV2027Z

Taps
256
Resistance (ohms)
10K
Number Of Circuits
4
Temperature Coefficient
45 ppm/°C Typical
Memory Type
Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Resistance In Ohms
10K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL90840WIV2027ZT1
Manufacturer:
INTERSIL
Quantity:
20 000
Low Noise, Low Power I
The ISL90840 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I
volatile Wiper Register (WR) that can be directly written to
and read by the user. The contents of the WR controls the
position of the wiper. When powered on the ISL90810’s
wiper will always commence at mid-scale (128 tap position).
The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Pinout
Ordering Information
NOTES:
2
ISL90840UIV2027Z (Notes 1 and 2)
ISL90840UIV2027
ISL90840UAV2027Z (Notes 1 and 2) ISL90840UA27Z
ISL90840WIV2027Z (Notes 1 and 2) ISL90840WI27Z
ISL90840WIV2027
ISL90840WAV2027Z (Notes 1 and 2) ISL90840WA27Z
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
2. Add “T2” suffix for tape and reel.
C bus interface. Each potentiometer has an associated
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PART NUMBER
RW3
GND
RW2
SDA
RH3
SCL
RH2
RL3
RL2
A2
(20 LD TSSOP)
1
2
3
4
5
6
7
8
9
10
TOP VIEW
ISL90840
®
1
2
20
19
18
17
16
15
14
13
12
11
ISL90840UI27Z
ISL90840UI27
ISL90840WI27
C
PART MARKING
Data Sheet
®
RW0
RL0
RH0
D.N.C.
VCC
A1
A0
RH1
RL1
RW1
Bus, 256 Taps
1-888-INTERSIL or 1-888-468-3774
Quad Digitally Controlled Potentiometers (XDCP™)
RESIST-ANCE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
OPTION
50k
50k
50k
10k
10k
10k
(Ω)
Features
• Four potentiometers in one package
• 256 resistor taps - 0.4% resolution
• I
• Power-on preset to mid-scale (128 tap position)
• Wiper resistance: 70Ω typical @ 3.3V
• Standby current <5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ, 10kΩ total resistance
• 20 Ld TSSOP package
• Pb-free plus anneal available (RoHS compliant)
November 14, 2006
|
- Three address pins, up to eight devices/bus
- Write/Read capability
2
Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
C serial interface
-40 to +105
-40 to +105
-40 to +85
-40 to +85
-40 to +85
-40 to +85
RANGE
TEMP
(°C)
All other trademarks mentioned are the property of their respective owners.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
20 Ld TSSOP (Pb-free)
20 Ld TSSOP
20 Ld TSSOP (Pb-free)
20 Ld TSSOP (Pb-free)
20 Ld TSSOP
20 Ld TSSOP (Pb-free)
PACKAGE
ISL90840
MDP0044
MDP0044
MDP0044
MDP0044
MDP0044
MDP0044
PKG. DWG #
FN8086.2

Related parts for ISL90840WIV2027Z

ISL90840WIV2027Z Summary of contents

Page 1

... PART MARKING ISL90840UIV2027Z (Notes 1 and 2) ISL90840UI27Z ISL90840UIV2027 ISL90840UI27 ISL90840UAV2027Z (Notes 1 and 2) ISL90840UA27Z ISL90840WIV2027Z (Notes 1 and 2) ISL90840WI27Z ISL90840WIV2027 ISL90840WI27 ISL90840WAV2027Z (Notes 1 and 2) ISL90840WA27Z NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...

Page 2

Functional Diagram SCL SDA A0 INTERFACE A1 A2 Block Diagram INTERFACE SDA SCL ISL90840 GND ...

Page 3

Pin Descriptions TSSOP PIN SYMBOL 1 RH3 2 RL3 3 RW3 SCL 6 SDA 7 GND 8 RW2 9 RL2 10 RH2 11 RW1 12 RL1 13 RH1 VCC 17 D.N.C. 18 ...

Page 4

Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at Any Digital Interface Pin With Respect to ...

Page 5

Analog Specifications Over recommended operating conditions unless otherwise stated. (Continued) SYMBOL PARAMETER TC Resistance temperature coefficient R (Note 17) Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER I V supply current (volatile CC1 CC write/read) I ...

Page 6

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER t STOP condition setup time SU:STO t STOP condition hod time for read, or HD:STO volatile only write t Output data hold time DH (Note 18) t ...

Page 7

SDA vs SCL Timing SCL t SU:STA t HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) A0, A1, and A2 Pin Timing START SCL SDA IN A0, A1 Typical Performance Curves 160 V =2.7, T=+85°C CC 140 V =2.7, ...

Page 8

Typical Performance Curves 0.2 V =5.5, T=-40°C CC 0.15 V =2.7, T=+25°C CC 0.1 0.05 0 -0.05 -0.1 V =5.5, T=+25°C CC -0.15 V =2.7, T=+85° 100 150 TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP ...

Page 9

Typical Performance Curves 1.5 1 2.7V 0.5 5.5V 0 -0.5 -1 -1.5 -40 - TEMPERATURE (°C) FIGURE 9. END TO END R % CHANGE vs TOTAL TEMPERATURE FOR 50kΩ ( -15 -25 32 ...

Page 10

Principles of Operation The ISL90840 is an integrated circuit incorporating four DCPs with their associated registers, and an I interface providing direct communication between a host and the potentiometers. DCP Description Each DCP is implemented with a combination of resistor ...

Page 11

SCL SDA START FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL FROM MASTER SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER 11 ISL90840 DATA DATA DATA STABLE CHANGE STABLE ...

Page 12

SIGNALS FROM THE MASTER SIGNAL AT SDA SIGNALS FROM THE ISL90840 S SIGNALS T FROM THE A IDENTIFICATION MASTER R BYTE WITH T R/W SIGNAL AT SDA SIGNALS FROM THE SLAVE Write ...

Page 13

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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