ISL90728WIE627Z-TK Intersil, ISL90728WIE627Z-TK Datasheet - Page 4

• Manufacturer Part Number: ISL90728WIE627Z-TK
• Description: IC XDCP 128-TAP 10OHM SC70-6
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL90728WIE627Z-TK

• Taps: 128
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SC-70-6, SC-88, SOT-363
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL90728WIE627Z-TK

Operating Specifications
SERIAL INTERFACE SPECIFICATIONS
t
Cpin (Note 16) SDA and SCL Pin Capacitance
DCP
t
R
V
Hysteresis
SYMBOL
I
t
t
t
t
t
t
CC
ComLkg
HD:DAT
SU:STO
HD:STO
(Note 16)
SU:STA
HD:STA
SU:DAT
t
t
I
f
t
HIGH
V
(Note 14) DCP Wiper Response Time
LOW
CC1
V
BUF
t
I
V
SCL
t
t
SB
t
AA
DH
Ramp
IN
OL
D
IH
IL
V
(Volatile write/read)
V
Common-Mode Leakage
V
Power-up Delay
SDA, and SCL Input Buffer LOW
Voltage
SDA, and SCL Input Buffer HIGH
Voltage
SDA and SCL Input Buffer Hysteresis
SDA Output Buffer LOW Voltage,
Sinking 4mA
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output Data
Valid
Time the Bus Must be Free Before the
Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
STOP Condition Hold Time for Read,
or Volatile Only Write
Output Data Hold Time
SDA and SCL Rise Time
CC
CC
CC
Supply Current
Current (standby)
Ramp Rate
PARAMETER
4
f
Read and Volatile Write States only)
V
Voltage at SDA pin to GND or V
SCL falling edge of last bit of DCP Data Byte to
wiper change
V
recall completed, and I
(Note 15)
(Note 15)
Any pulse narrower than the max spec is
suppressed.
SCL falling edge crossing 30% of V
exits the 30% to 70% of V
SDA crossing 70% of V
condition, to SDA crossing 70% of V
the following START condition.
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge. Both
crossing 70% of V
From SDA falling edge crossing 30% of V
SCL falling edge crossing 70% of V
From SDA exiting the 30% to 70% of V
window, to SCL rising edge crossing 30% of V
From SCL rising edge crossing 70% of V
SDA entering the 30% to 70% of V
From SCL rising edge crossing 70% of V
SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
From SCL falling edge crossing 30% of V
until SDA enters the 30% to 70% of V
From 30% to 70% of V
ISL90727, ISL90728
SCL
CC
CC
above V
= +5.5V, I
= 400kHz; SDA = Open; (for I
POR
TEST CONDITIONS
2
C Interface in Standby State
, to DCP Initial Value Register
CC
CC
.
.
2
C Interface in standby state
CC
CC
CC
CC
CC
during a STOP
window.
crossing.
crossing.
CC
CC
2
CC
CC
CC
C, Active,
CC
CC
, until SDA
window.
.
.
CC
during
window.
CC
CC
CC
CC
, to
,
to
to
CC
(Note 17)
0.1*Cb
0.05*
1300
1300
V
V
20 +
MIN
0.7*
-0.3
600
600
600
100
600
600
0.2
CC
CC
0
0
0
(Note 5)
TYP
500
(Note 17) UNIT
V
MAX
V
0.3*
200
500
400
900
250
0.3
0.4
CC
10
50
October 10, 2008
3
3
CC
+
FN8247.6
V/ms
kHz
µA
ms
µA
nA
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
V