TDA8754HL/11/C1,55 NXP Semiconductors, TDA8754HL/11/C1,55 Datasheet - Page 31

• Manufacturer Part Number: TDA8754HL/11/C1,55
• Description: IC TRPL 8BIT VIDEO ADC 144LQFP
• Manufacturer: NXP Semiconductors
• Type: Video ADCr

Specifications of TDA8754HL/11/C1,55

• Package / Case: 144-LQFP
• Resolution (bits): 8 b
• Sampling Rate (per Second): 110M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current: 180 mA
• Maximum Operating Temperature: + 70 C
• Maximum Power Dissipation: 1.3 W
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3594; 935272702551; TDA8754HL11BE-S

Philips Semiconductors
Table 41:
Table 42:
Table 43:
Table 44:
9397 750 14984
Product data sheet
Bit
7 to 5 PRECOAST[2:0]
4 to 0 POSTCOAST[4:0] programs the length (in numbers of pixel clocks) of the coast pulse after the edge of the vertical
Bit
7 to 4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Symbol
COAST - coast register (address 12h) bit allocation
COAST - coast register (address 12h) bit description
HSYNCSEL - horizontal sync selection register (address 13h) bit allocation
HSYNCSEL - horizontal sync selection register (address 13h) bit description
Symbol
-
TESTCNT
BYSEPA
HSSEL
HSS
COAST2
9.11 Coast register
9.12 Horizontal sync selection register
PRE
W
W
X
7
0
7
-
Remark: When POSTCOAST[4:0] = PRECOAST[2:0] = 0, then the coast pulse equals
the VSYNC input.
Description
programs the length (in numbers of pixel clocks) of the coast pulse before the edge of the
vertical sync signal
sync signal
COAST1
PRE
Description
not used
this bit is used to test the pixel counter
enables the sync separator for the PLL reference to be bypassed
enables either the HSYNC or CHSYNC input signal to be selected
enables either the HSYNC or CHSYNC input signal to be inverted
W
W
X
6
0
6
-
0 = normal mode
1 = test mode
0 = Hsync from the separator
1 = bypass of the sync separator
0 = HSYNC input
1 = CHSYNC input
0 = non-inverted
1 = inverted
COAST0
PRE
W
W
X
5
0
5
-
Rev. 06 — 16 June 2005
COAST4
POST
W
W
4
0
4
X
-
TESTCNT
COAST3
POST
W
W
3
0
3
0
Triple 8-bit video ADC up to 270 Msps
COAST2
BYSEPA
POST
W
W
2
0
2
1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
COAST1
HSSEL
POST
W
W
1
0
1
0
TDA8754
COAST0
POST
HSS
W
W
0
0
0
0
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