MAX186BCPP+ Maxim Integrated Products, MAX186BCPP+ Datasheet - Page 14
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MAX186BCPP+
Manufacturer Part Number
MAX186BCPP+
Description
IC DAS 8CH 12BIT T/H LP 20-DIP
Manufacturer
Maxim Integrated Products
Type
Data Acquisition System (DAS), ADCr
Datasheet
1.MAX188DCPP.pdf
(24 pages)
Specifications of MAX186BCPP+
Resolution (bits)
12 b
Sampling Rate (per Second)
133k
Data Interface
Serial
Voltage Supply Source
Dual ±
Voltage - Supply
±5V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
20-DIP (0.300", 7.62mm)
Number Of Adc Inputs
8
Architecture
SAR
Conversion Rate
133 KSPs
Resolution
12 bit
Input Type
Voltage
Interface Type
4-Wire (SPI, QSPI, MICROWIRE, TMS320)
Voltage Reference
Internal 4.096 V
Supply Voltage (max)
5 V
Maximum Power Dissipation
889 mW
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Input Signal Type
Single-Ended, Pseudo-Differential, Differential
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The falling edge of CS does not start a conversion on the
MAX186/MAX188. The first logic high clocked into DIN is
interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on the falling edge of
SCLK, after the eighth bit of the control byte (the PD0 bit)
is clocked into DIN. The start bit is defined as:
If a falling edge on CS forces a start bit before bit 5
(B5) becomes available, then the current conversion
will be terminated and a new one started. Thus, the
fastest the MAX186/MAX188 can run is 15 clocks per
conversion. Figure 11a shows the serial-interface timing
necessary to perform a conversion every 15 SCLK
cycles in external clock mode. If CS is low and SCLK is
continuous, guarantee a start bit by first clocking in 16
zeros.
Most microcontrollers require that conversions occur in
multiples of 8 SCLK clocks; 16 clocks per conversion
will typically be the fastest that a microcontroller can
drive the MAX186/MAX188. Figure 11b shows the
serial-interface timing necessary to perform a conver-
sion every 16 SCLK cycles in external clock mode.
Low-Power, 8-Channel,
Serial 12-Bit ADCs
Figure 10. Internal Clock Mode SSTRB Detailed Timing
14
The first high bit clocked into DIN with CS low any-
time the converter is idle, e.g. after V
The first high bit clocked into DIN after bit 5 of a
conversion in progress is clocked onto the DOUT pin.
______________________________________________________________________________________
SSTRB
SCLK
CS
PD0 CLOCK IN
OR
t
CSH
Data Framing
CC
is applied.
t
SSTRB
t
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
CONV
__________ Applications Information
When power is first applied and if SHDN is not pulled
low, internal power-on reset circuitry will activate the
MAX186/MAX188 in internal clock mode, ready to con-
vert with SSTRB = high. After the power supplies have
been stabilized, the internal reset time is 100µs and no
conversions should be performed during this phase.
SSTRB is high on power-up and, if CS is low, the first
logical 1 on DIN will be interpreted as a start bit. Until a
conversion takes place, DOUT will shift out zeros.
In addition to its shutdown function, the SHDN pin also
selects internal or external compensation. The compen-
sation affects both power-up time and maximum conver-
sion speed. Compensated or not, the minimum clock
rate is 100kHz due to droop on the sample-and-hold.
To select external compensation, float SHDN. See the
Typical Operating Circuit , which uses a 4.7µF capacitor at
VREF. A value of 4.7µF or greater ensures stability and
allows operation of the converter at the full clock speed of
2MHz. External compensation increases power-up time (see
the Choosing Power-Down Mode section, and Table 5).
Internal compensation requires no external capacitor at
VREF, and is selected by pulling SHDN high. Internal com-
pensation allows for shortest power-up times, but is only
available using an external clock and reduces the maxi-
mum clock rate to 400kHz.
Reference-Buffer Compensation
t
SCK
Power-On Reset
t
CSS