MAX1258BETM+ Maxim Integrated Products, MAX1258BETM+ Datasheet - Page 38

IC ADC/DAC 12BIT 48-TQFN

MAX1258BETM+

Manufacturer Part Number
MAX1258BETM+
Description
IC ADC/DAC 12BIT 48-TQFN
Manufacturer
Maxim Integrated Products
Type
ADC, DACr
Datasheet

Specifications of MAX1258BETM+

Resolution (bits)
12 b
Sampling Rate (per Second)
225k
Data Interface
Serial
Voltage Supply Source
Analog and Digital
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing speci-
fications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10)
38
______________________________________________________________________________________
SCLK
DOUT
NOTE: FOR THE MAX1220 GPIO WRITES, n = 16; FOR ALL DAC WRITES AND GPIO WRITES ON THE MAX1257/MAX1258, n = 24.
DIN
CS
t
CSPWH
t
DOE
t
t
CSS
DS
1
Dn-1
t
DH
D15
2
D7
Dn-2
t
DAC/GPIO Timing
CL
D14
D6
t
CH
3
Dn-3
t
DOT
D13
D5
4
Dn-4
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware LDAC command DAC-
register update. For a software-command DAC-register
update, t
lows the last data bit in the software command word.
D12
D4
5
Dn-5
S
is valid from the rising edge of CS, which fol-
D1
D1
32
16
8
D0
t
CSH
D0
t
DOD

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