HI5767/2CA Intersil, HI5767/2CA Datasheet - Page 15

• Manufacturer Part Number: HI5767/2CA
• Description: IC ADC 10-BIT 20MSPS 28-SSOP
• Manufacturer: Intersil

Specifications of HI5767/2CA

• Number Of Bits: 10
• Sampling Rate (per Second): 20M
• Data Interface: Parallel
• Number Of Converters: 8
• Power Dissipation (max): 310mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.150", 3.95mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Video Definitions
Differential Gain and Differential Phase are two commonly
found video specifications for characterizing the distortion of
a chrominance signal as it is offset through the input voltage
range of an ADC.
Differential Gain (DG)
Differential Gain is the peak difference in chrominance
amplitude (in percent) relative to the reference burst.
Differential Phase (DP)
Differential Phase is the peak difference in chrominance
phase (in degrees) relative to the reference burst.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (t
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (t
Aperture jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
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HI5767
Data Hold Time (t
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (t
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (t
After the analog sample is taken, the digital data representing
an analog input sample is output to the digital data bus on
the 7th cycle of the clock after the analog sample is taken.
This is due to the pipeline nature of the converter where the
analog sample has to ripple through the internal subconverter
stages. This delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital data lags the analog input sample by 7
sample clock cycles.
Power-Up Initialization
This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.
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