ADC12132CIMSA National Semiconductor, ADC12132CIMSA Datasheet - Page 31

• Manufacturer Part Number: ADC12132CIMSA
• Description: IC ADC 12BIT 20-SSOP
• Manufacturer: National Semiconductor

Specifications of ADC12132CIMSA

• Number Of Bits: 12
• Sampling Rate (per Second): 114k
• Data Interface: NSC MICROWIRE™, Serial
• Number Of Converters: 4
• Power Dissipation (max): 33mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC12132CIMSA

For pseudo-differential signed operation, the circuit of shows
a signal AC coupled to the ADC. This gives a digital output
range of −4096 to +4095. With a 2.5V reference, 1 LSB is
equal to 610 μV. Although the ADC is not production tested
with a 2.5V reference, when V
error typically will not change more than 0.1 LSB (see the
curves in the Typical Electrical Characteristics Section). With
the ADC set to an acquisition time of 10 clock periods, the
An alternative method for biasing pseudo-differential opera-
tion is to use the +2.5V from the LM4040 to bias any amplifier
circuits driving the ADC as shown in Figure 13. The value of
the resistor pull-up biasing the LM4040-2.5 will depend upon
the current required by the op amp biasing circuitry.
In the circuit of Figure 13, some voltage range is lost since the
amplifier will not be able to swing to +5V and GND with a
single +5V supply. Using an adjustable version of the LM4041
FIGURE 12. Pseudo-Differential Biasing with the Signal Source AC Coupled Directly into the ADC
A
+
and V
D
+
are +5.0V, linearity
FIGURE 11. Single-Ended Biasing
31
input biasing resistor needs to be 600Ω or less. Notice though
that the input coupling capacitor needs to be made fairly large
to bring down the high pass corner. Increasing the acquisition
time to 34 clock periods (with a 5 MHz CCLK frequency) would
allow the 600Ω to increase to 6k, which would set the high
pass corner at 26 Hz. Increasing R, to 6k would allow R
be 2k with a 1 μF coupling capacitor.
to set the full scale voltage at exactly 2.048V and a lower
grade LM4040D-2.5 to bias up everything to 2.5V as shown
in Figure 14 will allow the use of all the ADC's digital output
range of −4096 to +4095 while leaving plenty of head room
for the amplifier.
Fully differential operation is shown in Figure 15. One LSB for
this case is equal to (4.1V/4096) = 1 mV.
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