AD9640BCPZ-80 Analog Devices Inc, AD9640BCPZ-80 Datasheet - Page 5

• Manufacturer Part Number: AD9640BCPZ-80
• Description: IC ADC 14BIT 80MSPS 1.8V 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9640BCPZ-80

• Data Interface: Serial, SPI™
• Design Resources: Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Number Of Converters: 2
• Power Dissipation (max): 492mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Resolution (bits): 14bit
• Sampling Rate: 150MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Current: 233mA
• Digital Ic Case Style: CSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9640-150EBZ - BOARD EVALUATION AD9640 150MSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SPECIFICATIONS
ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
MATCHING CHARACTERISTIC
TEMPERATURE DRIFT
INTERNAL VOLTAGE REFERENCE
INPUT REFERRED NOISE
ANALOG INPUT
VREF INPUT RESISTANCE
POWER SUPPLIES
POWER CONSUMPTION
1
2
3
4
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.
The maximum limit applies to the combination of I
Standby power is measured with a dc input and with the CLK pins (CLK+, CLK
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Offset Error
Gain Error
Offset Error
Gain Error
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
VREF = 1.0 V
Input Span, VREF = 1.0 V
Input Capacitance
Supply Voltage
Supply Current
DC Input
Sine Wave Input
Sine Wave Input
Standby Power
Power-Down Power
AVDD, DVDD
DRVDD (CMOS Mode)
DRVDD (LVDS Mode)
I
I
I
I
I
AVDD
DVDD
DRVDD
DRVDD
DRVDD
1
1
, 3
,
1
1
1
3
(3.3 V CMOS)
(1.8 V CMOS)
(1.8 V LVDS)
4
1
1
(DRVDD = 1.8 V)
(DRVDD = 3.3 V)
2
1
1
Temperature
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AVDD
and I
DVDD
currents.
Min
14
1.7
1.7
1.7
Rev. B | Page 5 of 52
80/
AD9640ABCPZ-
−
AD9640BCPZ-80
) inactive (set to AVDD or AGND).
Typ
±0.3
±0.2
±0.4
±2.0
±0.3
±0.1
±95
1.3
1.8
3.3
1.8
±15
±2
7
2
8
6
233
26
27
12
54
452
487
550
52
2.5
Guaranteed
Max
±0.6
±3.0
±0.9
±5.0
±0.6
±0.5
±15
1.9
3.6
1.9
277
492
6
Min
14
1.7
1.7
1.7
105/
AD9640ABCPZ-
AD9640BCPZ-105
Typ
±0.3
±0.2
±0.4
±2.0
±0.4
±0.1
±15
±95
±2
7
1.3
2
8
6
1.8
3.3
1.8
310
34
35
18
55
603
645
730
68
2.5
Guaranteed
Max
±0.6
±3.0
±0.9
±5.0
±0.7
±0.5
±15
1.9
3.6
1.9
371
657
6
Unit
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
% FSR
% FSR
ppm/°C
ppm/°C
mV
mV
LSB rms
V p-p
pF
kΩ
V
V
V
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
AD9640