AD9222BCPZ-50 Analog Devices Inc, AD9222BCPZ-50 Datasheet - Page 6

IC ADC 12BIT 8CH 50MSPS 64LFCSP

AD9222BCPZ-50

Manufacturer Part Number
AD9222BCPZ-50
Description
IC ADC 12BIT 8CH 50MSPS 64LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9222BCPZ-50

Data Interface
Serial, SPI™
Number Of Bits
12
Sampling Rate (per Second)
50M
Number Of Converters
8
Power Dissipation (max)
760mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Resolution (bits)
12bit
Sampling Rate
50MSPS
Input Channel Type
Differential
Supply Voltage Range - Analog
1.7V To 1.9V
Supply Voltage Range - Digital
1.7V To 1.9V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9222-65EBZ - BOARD EVALUATION AD9222 65MSPSAD9222-50EBZ - BOARD EVALUATION FOR AD9222
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9222BCPZ-50
Manufacturer:
AD
Quantity:
1 001
Part Number:
AD9222BCPZ-50
Manufacturer:
ADI
Quantity:
280
AD9222
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
Parameter
CLOCK
OUTPUT PARAMETERS
APERTURE
1
2
3
4
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
This can be adjusted via the SPI interface.
Measurements were made using a part soldered to FR4 material.
t
SAMPLE
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (t
Clock Pulse Width Low (t
Propagation Delay (t
Rise Time (t
Fall Time (t
FCO Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Delay (t
DCO to FCO Delay (t
Data to Data Skew
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)
Pipeline Latency
Aperture Delay (t
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
(t
2
/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
DATA-MAX
1
F
R
) (20% to 80%)
− t
) (20% to 80%)
DATA-MIN
A
)
2
PD
DATA
, 3
FRAME
)
)
)
EL
CPD
4
EH
FCO
)
)
4
)
)
4
)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
25°C
25°C
Min
40
1.5
1.5
(t
− 300
(t
− 300
SAMPLE
SAMPLE
/24)
/24)
AD9222-40
Typ
12.5
12.5
2.3
300
300
2.3
t
(t
(t
(t
±50
600
375
8
750
<1
1
FCO
SAMPLE
SAMPLE
SAMPLE
+
/24)
/24)
/24)
Max
10
3.1
3.1
(t
+ 300
(t
+ 300
±200
SAMPLE
SAMPLE
Rev. D | Page 6 of 60
/24)
/24)
Min
50
1.5
1.5
(t
− 300
(t
− 300
SAMPLE
SAMPLE
/24)
/24)
AD9222-50
600
Typ
10.0
10.0
2.3
300
300
2.3
t
(t
(t
(t
±50
375
8
750
<1
1
FCO
SAMPLE
SAMPLE
SAMPLE
+
/24)
/24)
/24)
10
Max
3.1
3.1
(t
+ 300
(t
+ 300
±200
SAMPLE
SAMPLE
/24)
/24)
Min
65
1.5
1.5
(t
− 300
(t
− 300
SAMPLE
SAMPLE
/24)
/24)
AD9222-65
Typ
7.5
7.5
2.3
300
300
2.3
t
(t
(t
(t
±50
600
375
8
750
<1
1
FCO
SAMPLE
SAMPLE
SAMPLE
+
/24)
/24)
/24)
Max
10
3.1
3.1
(t
+ 300
(t
+ 300
±200
SAMPLE
SAMPLE
/24)
/24)
Unit
MSPS
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
ns
μs
CLK
cycles
ps
ps
rms
CLK
cycles

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