AD9228BCPZ-40 Analog Devices Inc, AD9228BCPZ-40 Datasheet - Page 34

• Manufacturer Part Number: AD9228BCPZ-40
• Description: IC ADC LVDS 12BIT QUAD 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9228BCPZ-40

• Data Interface: Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 40M
• Number Of Converters: 4
• Power Dissipation (max): 367mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 12bit
• Sampling Rate: 40MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9228-65EBZ - BOARD EVAL FOR AD9228
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9228
Table 16. Memory Map Register
Addr.
(Hex)
Chip Configuration Registers
00
01
02
Device Index and Transfer Registers
05
FF
ADC Functions
08
09
0D
Register Name
chip_port_config
chip_id
chip_grade
device_index_A
device_update
modes
clock
test_io
(MSB)
Bit 7
0
X
X
X
X
X
User test mode
00 = off (default)
01 = on, single alternate
10 = on, single once
11 = on, alternate once
Bit 6
LSB first
1 = on
0 = off
(default)
Child ID [6:4]
(identify device variants of Chip ID)
000 = 65 MSPS
001 = 40 MSPS
X
X
X
X
Bit 5
Soft
reset
1 = on
0 = off
(default)
Clock
Channel
DCO
1 = on
0 = off
(default)
X
X
X
Reset PN
long gen
1 = on
0 = off
(default)
(AD9228 = 0x02), (default)
8-bit Chip ID Bits [7:0]
Bit 4
1
Clock
Channel
FCO
1 = on
0 = off
(default)
X
X
X
Reset
PN short
gen
1 = on
0 = off
(default)
Rev. D | Page 34 of 56
Bit 3
1
X
Data
Channel
D
1 = on
(default)
0 = off
X
X
X
Output test mode—see
Digital Outputs and Timing
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
(format determined by output_mode)
Bit 2
Soft
reset
1 = on
0 = off
(default)
X
Data
Channel
C
1 = on
(default)
0 = off
X
Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
X
Bit 1
LSB first
1 = on
0 = off
(default)
X
Data
Channel
B
1 = on
(default)
0 = off
X
X
Table 9
section
in the
(LSB)
Bit 0
0
X
Data
Channel
A
1 = on
(default)
0 = off
SW
transfer
1 = on
0 = off
(default)
Duty
cycle
stabilizer
1 = on
(default)
0 = off
Default
Value
(Hex)
0x18
0x02
Read
only
0x0F
0x00
0x00
0x01
0x00
Default Notes/
Comments
The nibbles
should be
mirrored so that
LSB- or MSB-first
mode is set cor-
rectly regardless
of shift mode.
Default is unique
chip ID, different
for each device.
This is a read-
only register.
Child ID used to
differentiate
graded devices.
Bits are set to
determine which
on-chip device
receives the next
write command.
Synchronously
transfers data
from the master
shift register to
the slave.
Determines
various generic
modes of chip
operation.
Turns the
internal duty
cycle stabilizer
on and off.
When this reg-
ister is set, the
test data is placed
on the output
pins in place of
normal data.