AD7863AR-10REEL7 Analog Devices Inc, AD7863AR-10REEL7 Datasheet - Page 13

• Manufacturer Part Number: AD7863AR-10REEL7
• Description: IC ADC 14BIT DUAL 2CH 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7863AR-10REEL7

• Rohs Status: RoHS non-compliant
• Number Of Bits: 14
• Sampling Rate (per Second): 175k
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 94.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)

OPERATING MODES
MODE 1 OPERATION
Normal Power, High Sampling Performance
The timing diagram in Figure 7 is for optimum performance in
operating Mode 1 where the falling edge of CONVST starts
conversion and puts the track-and-hold amplifiers into their
hold mode. This falling edge of CONVST also causes the BUSY
signal to go high to indicate that a conversion is taking place.
The BUSY signal goes low when the conversion is complete,
which is 5.2 μs max after the falling edge of CONVST and new
data from this conversion is available in the output latch of the
AD7863. A read operation accesses this data. If the multiplexer
select A0 is low, the first and second read pulses after the first
conversion accesses the result from Channel A (V
respectively). The third and fourth read pulses, after the second
conversion and A0 high, access the result from Channel B (V
and V
parallel data bus with standard CS and RD signals. This data
read operation consists of a negative going pulse on the CS pin
combined with two negative going pulses on the RD pin (while
the CS is low), accessing the two 14-bit results. For the fastest
throughput rate the read operation takes 100 ns. The read
operation must be complete at least 400 ns before the falling
edge of the next CONVST and this gives a total time of 5.7 μs
for the full throughput time (equivalent to 175 kHz). This mode
of operation should be used for high sampling applications.
MODE 2 OPERATION
Power-Down, Auto-Sleep After Conversion
The timing diagram in Figure 11 is for optimum performance
in operating Mode 2 where the part automatically goes into
sleep mode once BUSY goes low after conversion and wakes up
before the next conversion takes place. This is achieved by
B2
, respectively). Data is read from the part via a 14-bit
CONVST
BUSY
DATA
RD
CS
A0
** WHEN USING AN INTERNAL REFERENCE, WAKE-UP TIME = 5ms.
* WHEN USING AN EXTERNAL REFERENCE, WAKE-UP TIME = 4.8µs.
t
CONV
t
3
= 5.2µs
Figure 11. Mode 2 Timing Diagram Where Automatic Sleep Function Is Initiated
V
A1
A1
and V
V
A2
A2
t
,
ACQ
Rev. B | Page 13 of 24
B1
t
8
t
CONV
= 5.2µs
keeping CONVST low at the end of the second conversion,
whereas it was high at the end of the second conversion for
Mode 1 operation.
The operation shown in Figure 11 shows how to access data
from both Channel A and Channel B, followed by the auto sleep
mode. One can also set up the timing to access data from
Channel A only or Channel B only (see the Read Options
section) and then go into auto sleep mode. The rising edge of
CONVST wakes up the part. This wake-up time is 4.8 μs when
using an external reference and 5 ms when using the internal
reference, at which point the track-and-hold amplifiers go into
their hold mode, provided the CONVST has gone low. The
conversion takes 5.2 μs after this giving a total of 10 μs (external
reference, 5.005 ms for internal reference) from the rising edge
of CONVST to the conversion being complete, which is
indicated by the BUSY going low.
Note that because the wake-up time from the rising edge of
CONVST is 4.8 μs, if the CONVST pulse width is greater than
5.2 μs the conversion takes more than the 10 μs (4.8 μs wake-up
time + 5.2 μs conversion time) shown in Figure 11 from the
rising edge of CONVST . This is because the track-and-hold
amplifiers go into their hold mode on the falling edge of
CONVST and the conversion does not complete for a further
5.2 μs. In this case, the BUSY is the best indicator of when the
conversion is complete. Even though the part is in sleep mode,
data can still be read from the part.
The read operation is identical to that in Mode 1 operation and
must also be complete at least 400 ns before the falling edge of
the next CONVST to allow the track-and-hold amplifiers to
have enough time to settle. This mode is very useful when the
part is converting at a slow rate because the power consumption
is significantly reduced from that of Mode 1 operation.
V
B1
V
B2
WAKE-UP TIME
4.8µs*/5ms**
t
3
AD7863